DPDK  18.11.0-rc3
rte_ethdev.h
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1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2017 Intel Corporation
3  */
4 
5 #ifndef _RTE_ETHDEV_H_
6 #define _RTE_ETHDEV_H_
7 
140 #ifdef __cplusplus
141 extern "C" {
142 #endif
143 
144 #include <stdint.h>
145 
146 /* Use this macro to check if LRO API is supported */
147 #define RTE_ETHDEV_HAS_LRO_SUPPORT
148 
149 #include <rte_compat.h>
150 #include <rte_log.h>
151 #include <rte_interrupts.h>
152 #include <rte_dev.h>
153 #include <rte_devargs.h>
154 #include <rte_errno.h>
155 #include <rte_common.h>
156 #include <rte_config.h>
157 
158 #include "rte_ether.h"
159 #include "rte_eth_ctrl.h"
160 #include "rte_dev_info.h"
161 
162 extern int rte_eth_dev_logtype;
163 
164 #define RTE_ETHDEV_LOG(level, ...) \
165  rte_log(RTE_LOG_ ## level, rte_eth_dev_logtype, "" __VA_ARGS__)
166 
167 struct rte_mbuf;
168 
185 int rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs);
186 
201 uint16_t rte_eth_iterator_next(struct rte_dev_iterator *iter);
202 
215 void rte_eth_iterator_cleanup(struct rte_dev_iterator *iter);
216 
230 #define RTE_ETH_FOREACH_MATCHING_DEV(id, devargs, iter) \
231  for (rte_eth_iterator_init(iter, devargs), \
232  id = rte_eth_iterator_next(iter); \
233  id != RTE_MAX_ETHPORTS; \
234  id = rte_eth_iterator_next(iter))
235 
243  uint64_t ipackets;
244  uint64_t opackets;
245  uint64_t ibytes;
246  uint64_t obytes;
247  uint64_t imissed;
251  uint64_t ierrors;
252  uint64_t oerrors;
253  uint64_t rx_nombuf;
254  uint64_t q_ipackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];
256  uint64_t q_opackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];
258  uint64_t q_ibytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];
260  uint64_t q_obytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];
262  uint64_t q_errors[RTE_ETHDEV_QUEUE_STAT_CNTRS];
264 };
265 
269 #define ETH_LINK_SPEED_AUTONEG (0 << 0)
270 #define ETH_LINK_SPEED_FIXED (1 << 0)
271 #define ETH_LINK_SPEED_10M_HD (1 << 1)
272 #define ETH_LINK_SPEED_10M (1 << 2)
273 #define ETH_LINK_SPEED_100M_HD (1 << 3)
274 #define ETH_LINK_SPEED_100M (1 << 4)
275 #define ETH_LINK_SPEED_1G (1 << 5)
276 #define ETH_LINK_SPEED_2_5G (1 << 6)
277 #define ETH_LINK_SPEED_5G (1 << 7)
278 #define ETH_LINK_SPEED_10G (1 << 8)
279 #define ETH_LINK_SPEED_20G (1 << 9)
280 #define ETH_LINK_SPEED_25G (1 << 10)
281 #define ETH_LINK_SPEED_40G (1 << 11)
282 #define ETH_LINK_SPEED_50G (1 << 12)
283 #define ETH_LINK_SPEED_56G (1 << 13)
284 #define ETH_LINK_SPEED_100G (1 << 14)
289 #define ETH_SPEED_NUM_NONE 0
290 #define ETH_SPEED_NUM_10M 10
291 #define ETH_SPEED_NUM_100M 100
292 #define ETH_SPEED_NUM_1G 1000
293 #define ETH_SPEED_NUM_2_5G 2500
294 #define ETH_SPEED_NUM_5G 5000
295 #define ETH_SPEED_NUM_10G 10000
296 #define ETH_SPEED_NUM_20G 20000
297 #define ETH_SPEED_NUM_25G 25000
298 #define ETH_SPEED_NUM_40G 40000
299 #define ETH_SPEED_NUM_50G 50000
300 #define ETH_SPEED_NUM_56G 56000
301 #define ETH_SPEED_NUM_100G 100000
306 __extension__
307 struct rte_eth_link {
308  uint32_t link_speed;
309  uint16_t link_duplex : 1;
310  uint16_t link_autoneg : 1;
311  uint16_t link_status : 1;
312 } __attribute__((aligned(8)));
314 /* Utility constants */
315 #define ETH_LINK_HALF_DUPLEX 0
316 #define ETH_LINK_FULL_DUPLEX 1
317 #define ETH_LINK_DOWN 0
318 #define ETH_LINK_UP 1
319 #define ETH_LINK_FIXED 0
320 #define ETH_LINK_AUTONEG 1
326 struct rte_eth_thresh {
327  uint8_t pthresh;
328  uint8_t hthresh;
329  uint8_t wthresh;
330 };
331 
335 #define ETH_MQ_RX_RSS_FLAG 0x1
336 #define ETH_MQ_RX_DCB_FLAG 0x2
337 #define ETH_MQ_RX_VMDQ_FLAG 0x4
338 
346 
350  ETH_MQ_RX_DCB = ETH_MQ_RX_DCB_FLAG,
352  ETH_MQ_RX_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG,
353 
355  ETH_MQ_RX_VMDQ_ONLY = ETH_MQ_RX_VMDQ_FLAG,
357  ETH_MQ_RX_VMDQ_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_VMDQ_FLAG,
359  ETH_MQ_RX_VMDQ_DCB = ETH_MQ_RX_VMDQ_FLAG | ETH_MQ_RX_DCB_FLAG,
362  ETH_MQ_RX_VMDQ_FLAG,
363 };
364 
368 #define ETH_RSS ETH_MQ_RX_RSS
369 #define VMDQ_DCB ETH_MQ_RX_VMDQ_DCB
370 #define ETH_DCB_RX ETH_MQ_RX_DCB
371 
381 };
382 
386 #define ETH_DCB_NONE ETH_MQ_TX_NONE
387 #define ETH_VMDQ_DCB_TX ETH_MQ_TX_VMDQ_DCB
388 #define ETH_DCB_TX ETH_MQ_TX_DCB
389 
396  uint32_t max_rx_pkt_len;
397  uint16_t split_hdr_size;
403  uint64_t offloads;
404 };
405 
411  ETH_VLAN_TYPE_UNKNOWN = 0,
414  ETH_VLAN_TYPE_MAX,
415 };
416 
422  uint64_t ids[64];
423 };
424 
443  uint8_t *rss_key;
444  uint8_t rss_key_len;
445  uint64_t rss_hf;
446 };
447 
448 /*
449  * The RSS offload types are defined based on flow types which are defined
450  * in rte_eth_ctrl.h. Different NIC hardwares may support different RSS offload
451  * types. The supported flow types or RSS offload types can be queried by
452  * rte_eth_dev_info_get().
453  */
454 #define ETH_RSS_IPV4 (1ULL << RTE_ETH_FLOW_IPV4)
455 #define ETH_RSS_FRAG_IPV4 (1ULL << RTE_ETH_FLOW_FRAG_IPV4)
456 #define ETH_RSS_NONFRAG_IPV4_TCP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP)
457 #define ETH_RSS_NONFRAG_IPV4_UDP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP)
458 #define ETH_RSS_NONFRAG_IPV4_SCTP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP)
459 #define ETH_RSS_NONFRAG_IPV4_OTHER (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER)
460 #define ETH_RSS_IPV6 (1ULL << RTE_ETH_FLOW_IPV6)
461 #define ETH_RSS_FRAG_IPV6 (1ULL << RTE_ETH_FLOW_FRAG_IPV6)
462 #define ETH_RSS_NONFRAG_IPV6_TCP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP)
463 #define ETH_RSS_NONFRAG_IPV6_UDP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP)
464 #define ETH_RSS_NONFRAG_IPV6_SCTP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP)
465 #define ETH_RSS_NONFRAG_IPV6_OTHER (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER)
466 #define ETH_RSS_L2_PAYLOAD (1ULL << RTE_ETH_FLOW_L2_PAYLOAD)
467 #define ETH_RSS_IPV6_EX (1ULL << RTE_ETH_FLOW_IPV6_EX)
468 #define ETH_RSS_IPV6_TCP_EX (1ULL << RTE_ETH_FLOW_IPV6_TCP_EX)
469 #define ETH_RSS_IPV6_UDP_EX (1ULL << RTE_ETH_FLOW_IPV6_UDP_EX)
470 #define ETH_RSS_PORT (1ULL << RTE_ETH_FLOW_PORT)
471 #define ETH_RSS_VXLAN (1ULL << RTE_ETH_FLOW_VXLAN)
472 #define ETH_RSS_GENEVE (1ULL << RTE_ETH_FLOW_GENEVE)
473 #define ETH_RSS_NVGRE (1ULL << RTE_ETH_FLOW_NVGRE)
474 
475 #define ETH_RSS_IP ( \
476  ETH_RSS_IPV4 | \
477  ETH_RSS_FRAG_IPV4 | \
478  ETH_RSS_NONFRAG_IPV4_OTHER | \
479  ETH_RSS_IPV6 | \
480  ETH_RSS_FRAG_IPV6 | \
481  ETH_RSS_NONFRAG_IPV6_OTHER | \
482  ETH_RSS_IPV6_EX)
483 
484 #define ETH_RSS_UDP ( \
485  ETH_RSS_NONFRAG_IPV4_UDP | \
486  ETH_RSS_NONFRAG_IPV6_UDP | \
487  ETH_RSS_IPV6_UDP_EX)
488 
489 #define ETH_RSS_TCP ( \
490  ETH_RSS_NONFRAG_IPV4_TCP | \
491  ETH_RSS_NONFRAG_IPV6_TCP | \
492  ETH_RSS_IPV6_TCP_EX)
493 
494 #define ETH_RSS_SCTP ( \
495  ETH_RSS_NONFRAG_IPV4_SCTP | \
496  ETH_RSS_NONFRAG_IPV6_SCTP)
497 
498 #define ETH_RSS_TUNNEL ( \
499  ETH_RSS_VXLAN | \
500  ETH_RSS_GENEVE | \
501  ETH_RSS_NVGRE)
502 
504 #define ETH_RSS_PROTO_MASK ( \
505  ETH_RSS_IPV4 | \
506  ETH_RSS_FRAG_IPV4 | \
507  ETH_RSS_NONFRAG_IPV4_TCP | \
508  ETH_RSS_NONFRAG_IPV4_UDP | \
509  ETH_RSS_NONFRAG_IPV4_SCTP | \
510  ETH_RSS_NONFRAG_IPV4_OTHER | \
511  ETH_RSS_IPV6 | \
512  ETH_RSS_FRAG_IPV6 | \
513  ETH_RSS_NONFRAG_IPV6_TCP | \
514  ETH_RSS_NONFRAG_IPV6_UDP | \
515  ETH_RSS_NONFRAG_IPV6_SCTP | \
516  ETH_RSS_NONFRAG_IPV6_OTHER | \
517  ETH_RSS_L2_PAYLOAD | \
518  ETH_RSS_IPV6_EX | \
519  ETH_RSS_IPV6_TCP_EX | \
520  ETH_RSS_IPV6_UDP_EX | \
521  ETH_RSS_PORT | \
522  ETH_RSS_VXLAN | \
523  ETH_RSS_GENEVE | \
524  ETH_RSS_NVGRE)
525 
526 /*
527  * Definitions used for redirection table entry size.
528  * Some RSS RETA sizes may not be supported by some drivers, check the
529  * documentation or the description of relevant functions for more details.
530  */
531 #define ETH_RSS_RETA_SIZE_64 64
532 #define ETH_RSS_RETA_SIZE_128 128
533 #define ETH_RSS_RETA_SIZE_256 256
534 #define ETH_RSS_RETA_SIZE_512 512
535 #define RTE_RETA_GROUP_SIZE 64
536 
537 /* Definitions used for VMDQ and DCB functionality */
538 #define ETH_VMDQ_MAX_VLAN_FILTERS 64
539 #define ETH_DCB_NUM_USER_PRIORITIES 8
540 #define ETH_VMDQ_DCB_NUM_QUEUES 128
541 #define ETH_DCB_NUM_QUEUES 128
543 /* DCB capability defines */
544 #define ETH_DCB_PG_SUPPORT 0x00000001
545 #define ETH_DCB_PFC_SUPPORT 0x00000002
547 /* Definitions used for VLAN Offload functionality */
548 #define ETH_VLAN_STRIP_OFFLOAD 0x0001
549 #define ETH_VLAN_FILTER_OFFLOAD 0x0002
550 #define ETH_VLAN_EXTEND_OFFLOAD 0x0004
552 /* Definitions used for mask VLAN setting */
553 #define ETH_VLAN_STRIP_MASK 0x0001
554 #define ETH_VLAN_FILTER_MASK 0x0002
555 #define ETH_VLAN_EXTEND_MASK 0x0004
556 #define ETH_VLAN_ID_MAX 0x0FFF
558 /* Definitions used for receive MAC address */
559 #define ETH_NUM_RECEIVE_MAC_ADDR 128
561 /* Definitions used for unicast hash */
562 #define ETH_VMDQ_NUM_UC_HASH_ARRAY 128
564 /* Definitions used for VMDQ pool rx mode setting */
565 #define ETH_VMDQ_ACCEPT_UNTAG 0x0001
566 #define ETH_VMDQ_ACCEPT_HASH_MC 0x0002
567 #define ETH_VMDQ_ACCEPT_HASH_UC 0x0004
568 #define ETH_VMDQ_ACCEPT_BROADCAST 0x0008
569 #define ETH_VMDQ_ACCEPT_MULTICAST 0x0010
572 #define ETH_MIRROR_MAX_VLANS 64
573 
574 #define ETH_MIRROR_VIRTUAL_POOL_UP 0x01
575 #define ETH_MIRROR_UPLINK_PORT 0x02
576 #define ETH_MIRROR_DOWNLINK_PORT 0x04
577 #define ETH_MIRROR_VLAN 0x08
578 #define ETH_MIRROR_VIRTUAL_POOL_DOWN 0x10
583 struct rte_eth_vlan_mirror {
584  uint64_t vlan_mask;
586  uint16_t vlan_id[ETH_MIRROR_MAX_VLANS];
587 };
588 
593  uint8_t rule_type;
594  uint8_t dst_pool;
595  uint64_t pool_mask;
598 };
599 
607  uint64_t mask;
609  uint16_t reta[RTE_RETA_GROUP_SIZE];
611 };
612 
618  ETH_4_TCS = 4,
620 };
621 
631 };
632 
633 /* This structure may be extended in future. */
634 struct rte_eth_dcb_rx_conf {
635  enum rte_eth_nb_tcs nb_tcs;
637  uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES];
638 };
639 
640 struct rte_eth_vmdq_dcb_tx_conf {
641  enum rte_eth_nb_pools nb_queue_pools;
643  uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES];
644 };
645 
646 struct rte_eth_dcb_tx_conf {
647  enum rte_eth_nb_tcs nb_tcs;
649  uint8_t dcb_tc[ETH_DCB_NUM_USER_PRIORITIES];
650 };
651 
652 struct rte_eth_vmdq_tx_conf {
653  enum rte_eth_nb_pools nb_queue_pools;
654 };
655 
670  uint8_t default_pool;
671  uint8_t nb_pool_maps;
672  struct {
673  uint16_t vlan_id;
674  uint64_t pools;
678 };
679 
701  uint8_t default_pool;
703  uint8_t nb_pool_maps;
704  uint32_t rx_mode;
705  struct {
706  uint16_t vlan_id;
707  uint64_t pools;
709 };
710 
721  uint64_t offloads;
722 
723  /* For i40e specifically */
724  uint16_t pvid;
725  __extension__
726  uint8_t hw_vlan_reject_tagged : 1,
732 };
733 
739  uint16_t rx_free_thresh;
740  uint8_t rx_drop_en;
747  uint64_t offloads;
748 };
749 
755  uint16_t tx_rs_thresh;
756  uint16_t tx_free_thresh;
765  uint64_t offloads;
766 };
767 
772  uint16_t nb_max;
773  uint16_t nb_min;
774  uint16_t nb_align;
784  uint16_t nb_seg_max;
785 
797  uint16_t nb_mtu_seg_max;
798 };
799 
808 };
809 
816  uint32_t high_water;
817  uint32_t low_water;
818  uint16_t pause_time;
819  uint16_t send_xon;
822  uint8_t autoneg;
823 };
824 
832  uint8_t priority;
833 };
834 
843 };
844 
852 };
853 
865  uint8_t drop_queue;
866  struct rte_eth_fdir_masks mask;
869 };
870 
879  uint16_t udp_port;
880  uint8_t prot_type;
881 };
882 
888  uint32_t lsc:1;
890  uint32_t rxq:1;
892  uint32_t rmv:1;
893 };
894 
900 struct rte_eth_conf {
901  uint32_t link_speeds;
910  uint32_t lpbk_mode;
915  struct {
919  struct rte_eth_dcb_rx_conf dcb_rx_conf;
923  } rx_adv_conf;
924  union {
925  struct rte_eth_vmdq_dcb_tx_conf vmdq_dcb_tx_conf;
927  struct rte_eth_dcb_tx_conf dcb_tx_conf;
929  struct rte_eth_vmdq_tx_conf vmdq_tx_conf;
931  } tx_adv_conf;
937 };
938 
942 #define DEV_RX_OFFLOAD_VLAN_STRIP 0x00000001
943 #define DEV_RX_OFFLOAD_IPV4_CKSUM 0x00000002
944 #define DEV_RX_OFFLOAD_UDP_CKSUM 0x00000004
945 #define DEV_RX_OFFLOAD_TCP_CKSUM 0x00000008
946 #define DEV_RX_OFFLOAD_TCP_LRO 0x00000010
947 #define DEV_RX_OFFLOAD_QINQ_STRIP 0x00000020
948 #define DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM 0x00000040
949 #define DEV_RX_OFFLOAD_MACSEC_STRIP 0x00000080
950 #define DEV_RX_OFFLOAD_HEADER_SPLIT 0x00000100
951 #define DEV_RX_OFFLOAD_VLAN_FILTER 0x00000200
952 #define DEV_RX_OFFLOAD_VLAN_EXTEND 0x00000400
953 #define DEV_RX_OFFLOAD_JUMBO_FRAME 0x00000800
954 #define DEV_RX_OFFLOAD_SCATTER 0x00002000
955 #define DEV_RX_OFFLOAD_TIMESTAMP 0x00004000
956 #define DEV_RX_OFFLOAD_SECURITY 0x00008000
957 #define DEV_RX_OFFLOAD_KEEP_CRC 0x00010000
958 #define DEV_RX_OFFLOAD_SCTP_CKSUM 0x00020000
959 #define DEV_RX_OFFLOAD_OUTER_UDP_CKSUM 0x00040000
960 
961 #define DEV_RX_OFFLOAD_CHECKSUM (DEV_RX_OFFLOAD_IPV4_CKSUM | \
962  DEV_RX_OFFLOAD_UDP_CKSUM | \
963  DEV_RX_OFFLOAD_TCP_CKSUM)
964 #define DEV_RX_OFFLOAD_VLAN (DEV_RX_OFFLOAD_VLAN_STRIP | \
965  DEV_RX_OFFLOAD_VLAN_FILTER | \
966  DEV_RX_OFFLOAD_VLAN_EXTEND)
967 
968 /*
969  * If new Rx offload capabilities are defined, they also must be
970  * mentioned in rte_rx_offload_names in rte_ethdev.c file.
971  */
972 
976 #define DEV_TX_OFFLOAD_VLAN_INSERT 0x00000001
977 #define DEV_TX_OFFLOAD_IPV4_CKSUM 0x00000002
978 #define DEV_TX_OFFLOAD_UDP_CKSUM 0x00000004
979 #define DEV_TX_OFFLOAD_TCP_CKSUM 0x00000008
980 #define DEV_TX_OFFLOAD_SCTP_CKSUM 0x00000010
981 #define DEV_TX_OFFLOAD_TCP_TSO 0x00000020
982 #define DEV_TX_OFFLOAD_UDP_TSO 0x00000040
983 #define DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM 0x00000080
984 #define DEV_TX_OFFLOAD_QINQ_INSERT 0x00000100
985 #define DEV_TX_OFFLOAD_VXLAN_TNL_TSO 0x00000200
986 #define DEV_TX_OFFLOAD_GRE_TNL_TSO 0x00000400
987 #define DEV_TX_OFFLOAD_IPIP_TNL_TSO 0x00000800
988 #define DEV_TX_OFFLOAD_GENEVE_TNL_TSO 0x00001000
989 #define DEV_TX_OFFLOAD_MACSEC_INSERT 0x00002000
990 #define DEV_TX_OFFLOAD_MT_LOCKFREE 0x00004000
991 
994 #define DEV_TX_OFFLOAD_MULTI_SEGS 0x00008000
995 
996 #define DEV_TX_OFFLOAD_MBUF_FAST_FREE 0x00010000
997 
1001 #define DEV_TX_OFFLOAD_SECURITY 0x00020000
1002 
1007 #define DEV_TX_OFFLOAD_UDP_TNL_TSO 0x00040000
1008 
1013 #define DEV_TX_OFFLOAD_IP_TNL_TSO 0x00080000
1014 
1015 #define DEV_TX_OFFLOAD_OUTER_UDP_CKSUM 0x00100000
1016 
1020 #define DEV_TX_OFFLOAD_MATCH_METADATA 0x00200000
1021 
1022 #define RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP 0x00000001
1023 
1024 #define RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP 0x00000002
1025 
1027 /*
1028  * If new Tx offload capabilities are defined, they also must be
1029  * mentioned in rte_tx_offload_names in rte_ethdev.c file.
1030  */
1031 
1032 /*
1033  * Fallback default preferred Rx/Tx port parameters.
1034  * These are used if an application requests default parameters
1035  * but the PMD does not provide preferred values.
1036  */
1037 #define RTE_ETH_DEV_FALLBACK_RX_RINGSIZE 512
1038 #define RTE_ETH_DEV_FALLBACK_TX_RINGSIZE 512
1039 #define RTE_ETH_DEV_FALLBACK_RX_NBQUEUES 1
1040 #define RTE_ETH_DEV_FALLBACK_TX_NBQUEUES 1
1041 
1048  uint16_t burst_size;
1049  uint16_t ring_size;
1050  uint16_t nb_queues;
1051 };
1052 
1057 #define RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID (0)
1058 
1063  const char *name;
1064  uint16_t domain_id;
1065  uint16_t port_id;
1073 };
1074 
1085  struct rte_device *device;
1086  const char *driver_name;
1087  unsigned int if_index;
1089  const uint32_t *dev_flags;
1090  uint32_t min_rx_bufsize;
1091  uint32_t max_rx_pktlen;
1092  uint16_t max_rx_queues;
1093  uint16_t max_tx_queues;
1094  uint32_t max_mac_addrs;
1095  uint32_t max_hash_mac_addrs;
1097  uint16_t max_vfs;
1098  uint16_t max_vmdq_pools;
1099  uint64_t rx_offload_capa;
1101  uint64_t tx_offload_capa;
1103  uint64_t rx_queue_offload_capa;
1105  uint64_t tx_queue_offload_capa;
1107  uint16_t reta_size;
1109  uint8_t hash_key_size;
1114  uint16_t vmdq_queue_base;
1115  uint16_t vmdq_queue_num;
1116  uint16_t vmdq_pool_base;
1119  uint32_t speed_capa;
1121  uint16_t nb_rx_queues;
1122  uint16_t nb_tx_queues;
1128  uint64_t dev_capa;
1134 };
1135 
1141  struct rte_mempool *mp;
1143  uint8_t scattered_rx;
1144  uint16_t nb_desc;
1146 
1153  uint16_t nb_desc;
1155 
1157 #define RTE_ETH_XSTATS_NAME_SIZE 64
1158 
1169  uint64_t id;
1170  uint64_t value;
1171 };
1172 
1182 };
1183 
1184 #define ETH_DCB_NUM_TCS 8
1185 #define ETH_MAX_VMDQ_POOL 64
1186 
1193  struct {
1194  uint8_t base;
1195  uint8_t nb_queue;
1196  } tc_rxq[ETH_MAX_VMDQ_POOL][ETH_DCB_NUM_TCS];
1198  struct {
1199  uint8_t base;
1200  uint8_t nb_queue;
1201  } tc_txq[ETH_MAX_VMDQ_POOL][ETH_DCB_NUM_TCS];
1202 };
1203 
1209  uint8_t nb_tcs;
1211  uint8_t tc_bws[ETH_DCB_NUM_TCS];
1214 };
1215 
1219 #define RTE_ETH_QUEUE_STATE_STOPPED 0
1220 #define RTE_ETH_QUEUE_STATE_STARTED 1
1221 
1222 #define RTE_ETH_ALL RTE_MAX_ETHPORTS
1223 
1224 /* Macros to check for valid port */
1225 #define RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, retval) do { \
1226  if (!rte_eth_dev_is_valid_port(port_id)) { \
1227  RTE_ETHDEV_LOG(ERR, "Invalid port_id=%u\n", port_id); \
1228  return retval; \
1229  } \
1230 } while (0)
1231 
1232 #define RTE_ETH_VALID_PORTID_OR_RET(port_id) do { \
1233  if (!rte_eth_dev_is_valid_port(port_id)) { \
1234  RTE_ETHDEV_LOG(ERR, "Invalid port_id=%u\n", port_id); \
1235  return; \
1236  } \
1237 } while (0)
1238 
1244 #define ETH_L2_TUNNEL_ENABLE_MASK 0x00000001
1245 
1246 #define ETH_L2_TUNNEL_INSERTION_MASK 0x00000002
1247 
1248 #define ETH_L2_TUNNEL_STRIPPING_MASK 0x00000004
1249 
1250 #define ETH_L2_TUNNEL_FORWARDING_MASK 0x00000008
1251 
1274 typedef uint16_t (*rte_rx_callback_fn)(uint16_t port_id, uint16_t queue,
1275  struct rte_mbuf *pkts[], uint16_t nb_pkts, uint16_t max_pkts,
1276  void *user_param);
1277 
1298 typedef uint16_t (*rte_tx_callback_fn)(uint16_t port_id, uint16_t queue,
1299  struct rte_mbuf *pkts[], uint16_t nb_pkts, void *user_param);
1300 
1313 };
1314 
1315 struct rte_eth_dev_sriov {
1316  uint8_t active;
1317  uint8_t nb_q_per_pool;
1318  uint16_t def_vmdq_idx;
1319  uint16_t def_pool_q_idx;
1320 };
1321 #define RTE_ETH_DEV_SRIOV(dev) ((dev)->data->sriov)
1322 
1323 #define RTE_ETH_NAME_MAX_LEN RTE_DEV_NAME_MAX_LEN
1324 
1325 #define RTE_ETH_DEV_NO_OWNER 0
1326 
1327 #define RTE_ETH_MAX_OWNER_NAME_LEN 64
1328 
1329 struct rte_eth_dev_owner {
1330  uint64_t id;
1331  char name[RTE_ETH_MAX_OWNER_NAME_LEN];
1332 };
1333 
1338 #define RTE_ETH_DEV_CLOSE_REMOVE 0x0001
1339 
1340 #define RTE_ETH_DEV_INTR_LSC 0x0002
1341 
1342 #define RTE_ETH_DEV_BONDED_SLAVE 0x0004
1343 
1344 #define RTE_ETH_DEV_INTR_RMV 0x0008
1345 
1346 #define RTE_ETH_DEV_REPRESENTOR 0x0010
1347 
1348 #define RTE_ETH_DEV_NOLIVE_MAC_ADDR 0x0020
1349 
1361 uint64_t rte_eth_find_next_owned_by(uint16_t port_id,
1362  const uint64_t owner_id);
1363 
1367 #define RTE_ETH_FOREACH_DEV_OWNED_BY(p, o) \
1368  for (p = rte_eth_find_next_owned_by(0, o); \
1369  (unsigned int)p < (unsigned int)RTE_MAX_ETHPORTS; \
1370  p = rte_eth_find_next_owned_by(p + 1, o))
1371 
1380 uint16_t rte_eth_find_next(uint16_t port_id);
1381 
1385 #define RTE_ETH_FOREACH_DEV(p) \
1386  RTE_ETH_FOREACH_DEV_OWNED_BY(p, RTE_ETH_DEV_NO_OWNER)
1387 
1388 
1402 int __rte_experimental rte_eth_dev_owner_new(uint64_t *owner_id);
1403 
1417 int __rte_experimental rte_eth_dev_owner_set(const uint16_t port_id,
1418  const struct rte_eth_dev_owner *owner);
1419 
1433 int __rte_experimental rte_eth_dev_owner_unset(const uint16_t port_id,
1434  const uint64_t owner_id);
1435 
1445 void __rte_experimental rte_eth_dev_owner_delete(const uint64_t owner_id);
1446 
1460 int __rte_experimental rte_eth_dev_owner_get(const uint16_t port_id,
1461  struct rte_eth_dev_owner *owner);
1462 
1475 __rte_deprecated
1476 uint16_t rte_eth_dev_count(void);
1477 
1488 uint16_t rte_eth_dev_count_avail(void);
1489 
1498 uint16_t __rte_experimental rte_eth_dev_count_total(void);
1499 
1511 uint32_t rte_eth_speed_bitflag(uint32_t speed, int duplex);
1512 
1521 const char *rte_eth_dev_rx_offload_name(uint64_t offload);
1522 
1531 const char *rte_eth_dev_tx_offload_name(uint64_t offload);
1532 
1572 int rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_queue,
1573  uint16_t nb_tx_queue, const struct rte_eth_conf *eth_conf);
1574 
1586 int __rte_experimental
1587 rte_eth_dev_is_removed(uint16_t port_id);
1588 
1638 int rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
1639  uint16_t nb_rx_desc, unsigned int socket_id,
1640  const struct rte_eth_rxconf *rx_conf,
1641  struct rte_mempool *mb_pool);
1642 
1691 int rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
1692  uint16_t nb_tx_desc, unsigned int socket_id,
1693  const struct rte_eth_txconf *tx_conf);
1694 
1705 int rte_eth_dev_socket_id(uint16_t port_id);
1706 
1716 int rte_eth_dev_is_valid_port(uint16_t port_id);
1717 
1734 int rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id);
1735 
1751 int rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id);
1752 
1769 int rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id);
1770 
1786 int rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id);
1787 
1807 int rte_eth_dev_start(uint16_t port_id);
1808 
1816 void rte_eth_dev_stop(uint16_t port_id);
1817 
1830 int rte_eth_dev_set_link_up(uint16_t port_id);
1831 
1841 int rte_eth_dev_set_link_down(uint16_t port_id);
1842 
1851 void rte_eth_dev_close(uint16_t port_id);
1852 
1890 int rte_eth_dev_reset(uint16_t port_id);
1891 
1898 void rte_eth_promiscuous_enable(uint16_t port_id);
1899 
1906 void rte_eth_promiscuous_disable(uint16_t port_id);
1907 
1918 int rte_eth_promiscuous_get(uint16_t port_id);
1919 
1926 void rte_eth_allmulticast_enable(uint16_t port_id);
1927 
1934 void rte_eth_allmulticast_disable(uint16_t port_id);
1935 
1946 int rte_eth_allmulticast_get(uint16_t port_id);
1947 
1959 void rte_eth_link_get(uint16_t port_id, struct rte_eth_link *link);
1960 
1972 void rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *link);
1973 
1991 int rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats);
1992 
2003 int rte_eth_stats_reset(uint16_t port_id);
2004 
2034 int rte_eth_xstats_get_names(uint16_t port_id,
2035  struct rte_eth_xstat_name *xstats_names,
2036  unsigned int size);
2037 
2067 int rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats,
2068  unsigned int n);
2069 
2092 int
2093 rte_eth_xstats_get_names_by_id(uint16_t port_id,
2094  struct rte_eth_xstat_name *xstats_names, unsigned int size,
2095  uint64_t *ids);
2096 
2120 int rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids,
2121  uint64_t *values, unsigned int size);
2122 
2141 int rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name,
2142  uint64_t *id);
2143 
2150 void rte_eth_xstats_reset(uint16_t port_id);
2151 
2169 int rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id,
2170  uint16_t tx_queue_id, uint8_t stat_idx);
2171 
2189 int rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id,
2190  uint16_t rx_queue_id,
2191  uint8_t stat_idx);
2192 
2202 void rte_eth_macaddr_get(uint16_t port_id, struct ether_addr *mac_addr);
2203 
2213 void rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info);
2214 
2234 int rte_eth_dev_fw_version_get(uint16_t port_id,
2235  char *fw_version, size_t fw_size);
2236 
2275 int rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask,
2276  uint32_t *ptypes, int num);
2277 
2289 int rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu);
2290 
2306 int rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu);
2307 
2327 int rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on);
2328 
2348 int rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id,
2349  int on);
2350 
2368 int rte_eth_dev_set_vlan_ether_type(uint16_t port_id,
2369  enum rte_vlan_type vlan_type,
2370  uint16_t tag_type);
2371 
2393 int rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask);
2394 
2407 int rte_eth_dev_get_vlan_offload(uint16_t port_id);
2408 
2423 int rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on);
2424 
2425 typedef void (*buffer_tx_error_fn)(struct rte_mbuf **unsent, uint16_t count,
2426  void *userdata);
2427 
2433  buffer_tx_error_fn error_callback;
2434  void *error_userdata;
2435  uint16_t size;
2436  uint16_t length;
2437  struct rte_mbuf *pkts[];
2439 };
2440 
2447 #define RTE_ETH_TX_BUFFER_SIZE(sz) \
2448  (sizeof(struct rte_eth_dev_tx_buffer) + (sz) * sizeof(struct rte_mbuf *))
2449 
2460 int
2461 rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size);
2462 
2487 int
2489  buffer_tx_error_fn callback, void *userdata);
2490 
2513 void
2514 rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent,
2515  void *userdata);
2516 
2540 void
2541 rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent,
2542  void *userdata);
2543 
2569 int
2570 rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt);
2571 
2587 };
2588 
2596  uint64_t metadata;
2610 };
2611 
2629 };
2630 
2631 typedef int (*rte_eth_dev_cb_fn)(uint16_t port_id,
2632  enum rte_eth_event_type event, void *cb_arg, void *ret_param);
2652 int rte_eth_dev_callback_register(uint16_t port_id,
2653  enum rte_eth_event_type event,
2654  rte_eth_dev_cb_fn cb_fn, void *cb_arg);
2655 
2674 int rte_eth_dev_callback_unregister(uint16_t port_id,
2675  enum rte_eth_event_type event,
2676  rte_eth_dev_cb_fn cb_fn, void *cb_arg);
2677 
2699 int rte_eth_dev_rx_intr_enable(uint16_t port_id, uint16_t queue_id);
2700 
2721 int rte_eth_dev_rx_intr_disable(uint16_t port_id, uint16_t queue_id);
2722 
2740 int rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data);
2741 
2763 int rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id,
2764  int epfd, int op, void *data);
2765 
2783 int __rte_experimental
2784 rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id);
2785 
2799 int rte_eth_led_on(uint16_t port_id);
2800 
2814 int rte_eth_led_off(uint16_t port_id);
2815 
2829 int rte_eth_dev_flow_ctrl_get(uint16_t port_id,
2830  struct rte_eth_fc_conf *fc_conf);
2831 
2846 int rte_eth_dev_flow_ctrl_set(uint16_t port_id,
2847  struct rte_eth_fc_conf *fc_conf);
2848 
2864 int rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,
2865  struct rte_eth_pfc_conf *pfc_conf);
2866 
2886 int rte_eth_dev_mac_addr_add(uint16_t port_id, struct ether_addr *mac_addr,
2887  uint32_t pool);
2888 
2902 int rte_eth_dev_mac_addr_remove(uint16_t port_id, struct ether_addr *mac_addr);
2903 
2917 int rte_eth_dev_default_mac_addr_set(uint16_t port_id,
2918  struct ether_addr *mac_addr);
2919 
2936 int rte_eth_dev_rss_reta_update(uint16_t port_id,
2937  struct rte_eth_rss_reta_entry64 *reta_conf,
2938  uint16_t reta_size);
2939 
2956 int rte_eth_dev_rss_reta_query(uint16_t port_id,
2957  struct rte_eth_rss_reta_entry64 *reta_conf,
2958  uint16_t reta_size);
2959 
2979 int rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct ether_addr *addr,
2980  uint8_t on);
2981 
3000 int rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on);
3001 
3024 int rte_eth_mirror_rule_set(uint16_t port_id,
3025  struct rte_eth_mirror_conf *mirror_conf,
3026  uint8_t rule_id,
3027  uint8_t on);
3028 
3043 int rte_eth_mirror_rule_reset(uint16_t port_id,
3044  uint8_t rule_id);
3045 
3062 int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx,
3063  uint16_t tx_rate);
3064 
3079 int rte_eth_dev_rss_hash_update(uint16_t port_id,
3080  struct rte_eth_rss_conf *rss_conf);
3081 
3096 int
3097 rte_eth_dev_rss_hash_conf_get(uint16_t port_id,
3098  struct rte_eth_rss_conf *rss_conf);
3099 
3118 int
3119 rte_eth_dev_udp_tunnel_port_add(uint16_t port_id,
3120  struct rte_eth_udp_tunnel *tunnel_udp);
3121 
3141 int
3142 rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id,
3143  struct rte_eth_udp_tunnel *tunnel_udp);
3144 
3159 int rte_eth_dev_filter_supported(uint16_t port_id,
3160  enum rte_filter_type filter_type);
3161 
3181 int rte_eth_dev_filter_ctrl(uint16_t port_id, enum rte_filter_type filter_type,
3182  enum rte_filter_op filter_op, void *arg);
3183 
3197 int rte_eth_dev_get_dcb_info(uint16_t port_id,
3198  struct rte_eth_dcb_info *dcb_info);
3199 
3200 struct rte_eth_rxtx_callback;
3201 
3226 const struct rte_eth_rxtx_callback *
3227 rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id,
3228  rte_rx_callback_fn fn, void *user_param);
3229 
3255 const struct rte_eth_rxtx_callback *
3256 rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id,
3257  rte_rx_callback_fn fn, void *user_param);
3258 
3283 const struct rte_eth_rxtx_callback *
3284 rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id,
3285  rte_tx_callback_fn fn, void *user_param);
3286 
3317 int rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id,
3318  const struct rte_eth_rxtx_callback *user_cb);
3319 
3350 int rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id,
3351  const struct rte_eth_rxtx_callback *user_cb);
3352 
3370 int rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id,
3371  struct rte_eth_rxq_info *qinfo);
3372 
3390 int rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id,
3391  struct rte_eth_txq_info *qinfo);
3392 
3410 int rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info);
3411 
3424 int rte_eth_dev_get_eeprom_length(uint16_t port_id);
3425 
3441 int rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info);
3442 
3458 int rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info);
3459 
3477 int __rte_experimental
3478 rte_eth_dev_get_module_info(uint16_t port_id,
3479  struct rte_eth_dev_module_info *modinfo);
3480 
3499 int __rte_experimental
3500 rte_eth_dev_get_module_eeprom(uint16_t port_id,
3501  struct rte_dev_eeprom_info *info);
3502 
3521 int rte_eth_dev_set_mc_addr_list(uint16_t port_id,
3522  struct ether_addr *mc_addr_set,
3523  uint32_t nb_mc_addr);
3524 
3537 int rte_eth_timesync_enable(uint16_t port_id);
3538 
3551 int rte_eth_timesync_disable(uint16_t port_id);
3552 
3571 int rte_eth_timesync_read_rx_timestamp(uint16_t port_id,
3572  struct timespec *timestamp, uint32_t flags);
3573 
3589 int rte_eth_timesync_read_tx_timestamp(uint16_t port_id,
3590  struct timespec *timestamp);
3591 
3609 int rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta);
3610 
3625 int rte_eth_timesync_read_time(uint16_t port_id, struct timespec *time);
3626 
3645 int rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *time);
3646 
3662 int
3663 rte_eth_dev_l2_tunnel_eth_type_conf(uint16_t port_id,
3664  struct rte_eth_l2_tunnel_conf *l2_tunnel);
3665 
3690 int
3691 rte_eth_dev_l2_tunnel_offload_set(uint16_t port_id,
3692  struct rte_eth_l2_tunnel_conf *l2_tunnel,
3693  uint32_t mask,
3694  uint8_t en);
3695 
3711 int
3712 rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id);
3713 
3728 int
3729 rte_eth_dev_get_name_by_port(uint16_t port_id, char *name);
3730 
3747 int rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id,
3748  uint16_t *nb_rx_desc,
3749  uint16_t *nb_tx_desc);
3750 
3765 int
3766 rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool);
3767 
3777 void *
3778 rte_eth_dev_get_sec_ctx(uint16_t port_id);
3779 
3780 
3781 #include <rte_ethdev_core.h>
3782 
3865 static inline uint16_t
3866 rte_eth_rx_burst(uint16_t port_id, uint16_t queue_id,
3867  struct rte_mbuf **rx_pkts, const uint16_t nb_pkts)
3868 {
3869  struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3870  uint16_t nb_rx;
3871 
3872 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3873  RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
3874  RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, 0);
3875 
3876  if (queue_id >= dev->data->nb_rx_queues) {
3877  RTE_ETHDEV_LOG(ERR, "Invalid RX queue_id=%u\n", queue_id);
3878  return 0;
3879  }
3880 #endif
3881  nb_rx = (*dev->rx_pkt_burst)(dev->data->rx_queues[queue_id],
3882  rx_pkts, nb_pkts);
3883 
3884 #ifdef RTE_ETHDEV_RXTX_CALLBACKS
3885  if (unlikely(dev->post_rx_burst_cbs[queue_id] != NULL)) {
3886  struct rte_eth_rxtx_callback *cb =
3887  dev->post_rx_burst_cbs[queue_id];
3888 
3889  do {
3890  nb_rx = cb->fn.rx(port_id, queue_id, rx_pkts, nb_rx,
3891  nb_pkts, cb->param);
3892  cb = cb->next;
3893  } while (cb != NULL);
3894  }
3895 #endif
3896 
3897  return nb_rx;
3898 }
3899 
3912 static inline int
3913 rte_eth_rx_queue_count(uint16_t port_id, uint16_t queue_id)
3914 {
3915  struct rte_eth_dev *dev;
3916 
3917  RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
3918  dev = &rte_eth_devices[port_id];
3919  RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_count, -ENOTSUP);
3920  if (queue_id >= dev->data->nb_rx_queues)
3921  return -EINVAL;
3922 
3923  return (int)(*dev->dev_ops->rx_queue_count)(dev, queue_id);
3924 }
3925 
3941 static inline int
3942 rte_eth_rx_descriptor_done(uint16_t port_id, uint16_t queue_id, uint16_t offset)
3943 {
3944  struct rte_eth_dev *dev = &rte_eth_devices[port_id];
3945  RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3946  RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_descriptor_done, -ENOTSUP);
3947  return (*dev->dev_ops->rx_descriptor_done)( \
3948  dev->data->rx_queues[queue_id], offset);
3949 }
3950 
3951 #define RTE_ETH_RX_DESC_AVAIL 0
3952 #define RTE_ETH_RX_DESC_DONE 1
3953 #define RTE_ETH_RX_DESC_UNAVAIL 2
3988 static inline int
3989 rte_eth_rx_descriptor_status(uint16_t port_id, uint16_t queue_id,
3990  uint16_t offset)
3991 {
3992  struct rte_eth_dev *dev;
3993  void *rxq;
3994 
3995 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
3996  RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
3997 #endif
3998  dev = &rte_eth_devices[port_id];
3999 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4000  if (queue_id >= dev->data->nb_rx_queues)
4001  return -ENODEV;
4002 #endif
4003  RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_descriptor_status, -ENOTSUP);
4004  rxq = dev->data->rx_queues[queue_id];
4005 
4006  return (*dev->dev_ops->rx_descriptor_status)(rxq, offset);
4007 }
4008 
4009 #define RTE_ETH_TX_DESC_FULL 0
4010 #define RTE_ETH_TX_DESC_DONE 1
4011 #define RTE_ETH_TX_DESC_UNAVAIL 2
4046 static inline int rte_eth_tx_descriptor_status(uint16_t port_id,
4047  uint16_t queue_id, uint16_t offset)
4048 {
4049  struct rte_eth_dev *dev;
4050  void *txq;
4051 
4052 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4053  RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4054 #endif
4055  dev = &rte_eth_devices[port_id];
4056 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4057  if (queue_id >= dev->data->nb_tx_queues)
4058  return -ENODEV;
4059 #endif
4060  RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_descriptor_status, -ENOTSUP);
4061  txq = dev->data->tx_queues[queue_id];
4062 
4063  return (*dev->dev_ops->tx_descriptor_status)(txq, offset);
4064 }
4065 
4132 static inline uint16_t
4133 rte_eth_tx_burst(uint16_t port_id, uint16_t queue_id,
4134  struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
4135 {
4136  struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4137 
4138 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4139  RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
4140  RTE_FUNC_PTR_OR_ERR_RET(*dev->tx_pkt_burst, 0);
4141 
4142  if (queue_id >= dev->data->nb_tx_queues) {
4143  RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id);
4144  return 0;
4145  }
4146 #endif
4147 
4148 #ifdef RTE_ETHDEV_RXTX_CALLBACKS
4149  struct rte_eth_rxtx_callback *cb = dev->pre_tx_burst_cbs[queue_id];
4150 
4151  if (unlikely(cb != NULL)) {
4152  do {
4153  nb_pkts = cb->fn.tx(port_id, queue_id, tx_pkts, nb_pkts,
4154  cb->param);
4155  cb = cb->next;
4156  } while (cb != NULL);
4157  }
4158 #endif
4159 
4160  return (*dev->tx_pkt_burst)(dev->data->tx_queues[queue_id], tx_pkts, nb_pkts);
4161 }
4162 
4219 #ifndef RTE_ETHDEV_TX_PREPARE_NOOP
4220 
4221 static inline uint16_t
4222 rte_eth_tx_prepare(uint16_t port_id, uint16_t queue_id,
4223  struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
4224 {
4225  struct rte_eth_dev *dev;
4226 
4227 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4228  if (!rte_eth_dev_is_valid_port(port_id)) {
4229  RTE_ETHDEV_LOG(ERR, "Invalid TX port_id=%u\n", port_id);
4230  rte_errno = -EINVAL;
4231  return 0;
4232  }
4233 #endif
4234 
4235  dev = &rte_eth_devices[port_id];
4236 
4237 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4238  if (queue_id >= dev->data->nb_tx_queues) {
4239  RTE_ETHDEV_LOG(ERR, "Invalid TX queue_id=%u\n", queue_id);
4240  rte_errno = -EINVAL;
4241  return 0;
4242  }
4243 #endif
4244 
4245  if (!dev->tx_pkt_prepare)
4246  return nb_pkts;
4247 
4248  return (*dev->tx_pkt_prepare)(dev->data->tx_queues[queue_id],
4249  tx_pkts, nb_pkts);
4250 }
4251 
4252 #else
4253 
4254 /*
4255  * Native NOOP operation for compilation targets which doesn't require any
4256  * preparations steps, and functional NOOP may introduce unnecessary performance
4257  * drop.
4258  *
4259  * Generally this is not a good idea to turn it on globally and didn't should
4260  * be used if behavior of tx_preparation can change.
4261  */
4262 
4263 static inline uint16_t
4264 rte_eth_tx_prepare(__rte_unused uint16_t port_id,
4265  __rte_unused uint16_t queue_id,
4266  __rte_unused struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
4267 {
4268  return nb_pkts;
4269 }
4270 
4271 #endif
4272 
4295 static inline uint16_t
4296 rte_eth_tx_buffer_flush(uint16_t port_id, uint16_t queue_id,
4297  struct rte_eth_dev_tx_buffer *buffer)
4298 {
4299  uint16_t sent;
4300  uint16_t to_send = buffer->length;
4301 
4302  if (to_send == 0)
4303  return 0;
4304 
4305  sent = rte_eth_tx_burst(port_id, queue_id, buffer->pkts, to_send);
4306 
4307  buffer->length = 0;
4308 
4309  /* All packets sent, or to be dealt with by callback below */
4310  if (unlikely(sent != to_send))
4311  buffer->error_callback(&buffer->pkts[sent],
4312  (uint16_t)(to_send - sent),
4313  buffer->error_userdata);
4314 
4315  return sent;
4316 }
4317 
4348 static __rte_always_inline uint16_t
4349 rte_eth_tx_buffer(uint16_t port_id, uint16_t queue_id,
4350  struct rte_eth_dev_tx_buffer *buffer, struct rte_mbuf *tx_pkt)
4351 {
4352  buffer->pkts[buffer->length++] = tx_pkt;
4353  if (buffer->length < buffer->size)
4354  return 0;
4355 
4356  return rte_eth_tx_buffer_flush(port_id, queue_id, buffer);
4357 }
4358 
4359 #ifdef __cplusplus
4360 }
4361 #endif
4362 
4363 #endif /* _RTE_ETHDEV_H_ */