8#ifndef _RTE_EVENTDEV_H_
9#define _RTE_EVENTDEV_H_
242#include <rte_compat.h>
253#define RTE_EVENT_DEV_CAP_QUEUE_QOS RTE_BIT32(0)
271#define RTE_EVENT_DEV_CAP_EVENT_QOS RTE_BIT32(1)
285#define RTE_EVENT_DEV_CAP_DISTRIBUTED_SCHED RTE_BIT32(2)
295#define RTE_EVENT_DEV_CAP_QUEUE_ALL_TYPES RTE_BIT32(3)
319#define RTE_EVENT_DEV_CAP_BURST_MODE RTE_BIT32(4)
330#define RTE_EVENT_DEV_CAP_IMPLICIT_RELEASE_DISABLE RTE_BIT32(5)
343#define RTE_EVENT_DEV_CAP_NONSEQ_MODE RTE_BIT32(6)
355#define RTE_EVENT_DEV_CAP_RUNTIME_PORT_LINK RTE_BIT32(7)
366#define RTE_EVENT_DEV_CAP_MULTIPLE_QUEUE_PORT RTE_BIT32(8)
376#define RTE_EVENT_DEV_CAP_CARRY_FLOW_ID RTE_BIT32(9)
385#define RTE_EVENT_DEV_CAP_MAINTENANCE_FREE RTE_BIT32(10)
398#define RTE_EVENT_DEV_CAP_RUNTIME_QUEUE_ATTR RTE_BIT32(11)
408#define RTE_EVENT_DEV_CAP_PROFILE_LINK RTE_BIT32(12)
422#define RTE_EVENT_DEV_CAP_ATOMIC RTE_BIT32(13)
430#define RTE_EVENT_DEV_CAP_ORDERED RTE_BIT32(14)
438#define RTE_EVENT_DEV_CAP_PARALLEL RTE_BIT32(15)
446#define RTE_EVENT_DEV_CAP_INDEPENDENT_ENQ RTE_BIT32(16)
465#define RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE RTE_BIT32(17)
477#define RTE_EVENT_DEV_CAP_EVENT_PRESCHEDULE_ADAPTIVE RTE_BIT32(18)
489#define RTE_EVENT_DEV_CAP_PER_PORT_PRESCHEDULE RTE_BIT32(19)
499#define RTE_EVENT_DEV_CAP_PRESCHEDULE_EXPLICIT RTE_BIT32(20)
509#define RTE_EVENT_DEV_PRIORITY_HIGHEST 0
516#define RTE_EVENT_DEV_PRIORITY_NORMAL 128
523#define RTE_EVENT_DEV_PRIORITY_LOWEST 255
532#define RTE_EVENT_QUEUE_WEIGHT_HIGHEST 255
538#define RTE_EVENT_QUEUE_WEIGHT_LOWEST 0
546#define RTE_EVENT_QUEUE_AFFINITY_HIGHEST 255
552#define RTE_EVENT_QUEUE_AFFINITY_LOWEST 0
709#define RTE_EVENT_DEV_ATTR_PORT_COUNT 0
713#define RTE_EVENT_DEV_ATTR_QUEUE_COUNT 1
717#define RTE_EVENT_DEV_ATTR_STARTED 2
733 uint32_t *attr_value);
737#define RTE_EVENT_DEV_CFG_PER_DEQUEUE_TIMEOUT RTE_BIT32(0)
877#define RTE_EVENT_QUEUE_CFG_ALL_TYPES RTE_BIT32(0)
891#define RTE_EVENT_QUEUE_CFG_SINGLE_LINK RTE_BIT32(1)
1041#define RTE_EVENT_QUEUE_ATTR_PRIORITY 0
1045#define RTE_EVENT_QUEUE_ATTR_NB_ATOMIC_FLOWS 1
1049#define RTE_EVENT_QUEUE_ATTR_NB_ATOMIC_ORDER_SEQUENCES 2
1053#define RTE_EVENT_QUEUE_ATTR_EVENT_QUEUE_CFG 3
1057#define RTE_EVENT_QUEUE_ATTR_SCHEDULE_TYPE 4
1061#define RTE_EVENT_QUEUE_ATTR_WEIGHT 5
1065#define RTE_EVENT_QUEUE_ATTR_AFFINITY 6
1089 uint32_t *attr_value);
1112 uint64_t attr_value);
1117#define RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL RTE_BIT32(0)
1124#define RTE_EVENT_PORT_CFG_SINGLE_LINK RTE_BIT32(1)
1132#define RTE_EVENT_PORT_CFG_HINT_PRODUCER RTE_BIT32(2)
1142#define RTE_EVENT_PORT_CFG_HINT_CONSUMER RTE_BIT32(3)
1153#define RTE_EVENT_PORT_CFG_HINT_WORKER RTE_BIT32(4)
1164#define RTE_EVENT_PORT_CFG_INDEPENDENT_ENQ RTE_BIT32(5)
1307#define RTE_EVENT_PORT_ATTR_ENQ_DEPTH 0
1311#define RTE_EVENT_PORT_ATTR_DEQ_DEPTH 1
1317#define RTE_EVENT_PORT_ATTR_NEW_EVENT_THRESHOLD 2
1321#define RTE_EVENT_PORT_ATTR_IMPLICIT_RELEASE_DISABLE 3
1342 uint32_t *attr_value);
1445 uint16_t elem_offset : 12;
1449 uint16_t attr_valid : 1;
1467 uint64_t impl_opaque;
1495#define RTE_SCHED_TYPE_ORDERED 0
1533#define RTE_SCHED_TYPE_ATOMIC 1
1560#define RTE_SCHED_TYPE_PARALLEL 2
1574#define RTE_EVENT_TYPE_ETHDEV 0x0
1576#define RTE_EVENT_TYPE_CRYPTODEV 0x1
1578#define RTE_EVENT_TYPE_TIMER 0x2
1580#define RTE_EVENT_TYPE_CPU 0x3
1584#define RTE_EVENT_TYPE_ETH_RX_ADAPTER 0x4
1586#define RTE_EVENT_TYPE_DMADEV 0x5
1588#define RTE_EVENT_TYPE_VECTOR 0x8
1600#define RTE_EVENT_TYPE_ETHDEV_VECTOR \
1601 (RTE_EVENT_TYPE_VECTOR | RTE_EVENT_TYPE_ETHDEV)
1603#define RTE_EVENT_TYPE_CPU_VECTOR (RTE_EVENT_TYPE_VECTOR | RTE_EVENT_TYPE_CPU)
1605#define RTE_EVENT_TYPE_ETH_RX_ADAPTER_VECTOR \
1606 (RTE_EVENT_TYPE_VECTOR | RTE_EVENT_TYPE_ETH_RX_ADAPTER)
1608#define RTE_EVENT_TYPE_CRYPTODEV_VECTOR \
1609 (RTE_EVENT_TYPE_VECTOR | RTE_EVENT_TYPE_CRYPTODEV)
1612#define RTE_EVENT_TYPE_MAX 0x10
1616#define RTE_EVENT_OP_NEW 0
1621#define RTE_EVENT_OP_FORWARD 1
1633#define RTE_EVENT_OP_RELEASE 2
1799#define RTE_EVENT_ETH_RX_ADAPTER_CAP_INTERNAL_PORT 0x1
1803#define RTE_EVENT_ETH_RX_ADAPTER_CAP_MULTI_EVENTQ 0x2
1807#define RTE_EVENT_ETH_RX_ADAPTER_CAP_OVERRIDE_FLOW_ID 0x4
1814#define RTE_EVENT_ETH_RX_ADAPTER_CAP_EVENT_VECTOR 0x8
1839#define RTE_EVENT_TIMER_ADAPTER_CAP_INTERNAL_PORT RTE_BIT32(0)
1842#define RTE_EVENT_TIMER_ADAPTER_CAP_PERIODIC RTE_BIT32(1)
1862#define RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_NEW 0x1
1869#define RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_OP_FWD 0x2
1876#define RTE_EVENT_CRYPTO_ADAPTER_CAP_INTERNAL_PORT_QP_EV_BIND 0x4
1881#define RTE_EVENT_CRYPTO_ADAPTER_CAP_SESSION_PRIVATE_DATA 0x8
1886#define RTE_EVENT_CRYPTO_ADAPTER_CAP_EVENT_VECTOR 0x10
1915#define RTE_EVENT_DMA_ADAPTER_CAP_INTERNAL_PORT_OP_NEW 0x1
1922#define RTE_EVENT_DMA_ADAPTER_CAP_INTERNAL_PORT_OP_FWD 0x2
1929#define RTE_EVENT_DMA_ADAPTER_CAP_INTERNAL_PORT_VCHAN_EV_BIND 0x4
1957#define RTE_EVENT_ETH_TX_ADAPTER_CAP_INTERNAL_PORT 0x1
1960#define RTE_EVENT_ETH_TX_ADAPTER_CAP_EVENT_VECTOR 0x2
2011 uint64_t *timeout_ticks);
2078 const uint8_t queues[],
const uint8_t priorities[],
2126 uint8_t queues[], uint16_t nb_unlinks);
2203 const uint8_t priorities[], uint16_t nb_links, uint8_t profile_id);
2256 uint16_t nb_unlinks, uint8_t profile_id);
2310 uint8_t queues[], uint8_t priorities[]);
2346 uint8_t priorities[], uint8_t profile_id);
2383#define RTE_EVENT_DEV_XSTATS_NAME_SIZE 64
2389 RTE_EVENT_DEV_XSTATS_DEVICE,
2390 RTE_EVENT_DEV_XSTATS_PORT,
2391 RTE_EVENT_DEV_XSTATS_QUEUE,
2439 uint8_t queue_port_id,
2473 uint8_t queue_port_id,
2474 const uint64_t ids[],
2475 uint64_t values[],
unsigned int n);
2520 int16_t queue_port_id,
2521 const uint64_t ids[],
2571#include <rte_eventdev_core.h>
2578__rte_event_enqueue_burst(uint8_t dev_id, uint8_t port_id,
2579 const struct rte_event ev[], uint16_t nb_events,
2580 const event_enqueue_burst_t fn)
2582 const struct rte_event_fp_ops *fp_ops;
2585 fp_ops = &rte_event_fp_ops[dev_id];
2586 port = fp_ops->data[port_id];
2587#ifdef RTE_LIBRTE_EVENTDEV_DEBUG
2588 if (dev_id >= RTE_EVENT_MAX_DEVS ||
2589 port_id >= RTE_EVENT_MAX_PORTS_PER_DEV) {
2599 rte_eventdev_trace_enq_burst(dev_id, port_id, ev, nb_events, (
void *)fn);
2601 return fn(port, ev, nb_events);
2647static inline uint16_t
2649 const struct rte_event ev[], uint16_t nb_events)
2651 const struct rte_event_fp_ops *fp_ops;
2653 fp_ops = &rte_event_fp_ops[dev_id];
2654 return __rte_event_enqueue_burst(dev_id, port_id, ev, nb_events,
2655 fp_ops->enqueue_burst);
2699static inline uint16_t
2701 const struct rte_event ev[], uint16_t nb_events)
2703 const struct rte_event_fp_ops *fp_ops;
2705 fp_ops = &rte_event_fp_ops[dev_id];
2706 return __rte_event_enqueue_burst(dev_id, port_id, ev, nb_events,
2707 fp_ops->enqueue_new_burst);
2751static inline uint16_t
2753 const struct rte_event ev[], uint16_t nb_events)
2755 const struct rte_event_fp_ops *fp_ops;
2757 fp_ops = &rte_event_fp_ops[dev_id];
2758 return __rte_event_enqueue_burst(dev_id, port_id, ev, nb_events,
2759 fp_ops->enqueue_forward_burst);
2828static inline uint16_t
2830 uint16_t nb_events, uint64_t timeout_ticks)
2832 const struct rte_event_fp_ops *fp_ops;
2835 fp_ops = &rte_event_fp_ops[dev_id];
2836 port = fp_ops->data[port_id];
2837#ifdef RTE_LIBRTE_EVENTDEV_DEBUG
2838 if (dev_id >= RTE_EVENT_MAX_DEVS ||
2839 port_id >= RTE_EVENT_MAX_PORTS_PER_DEV) {
2849 rte_eventdev_trace_deq_burst(dev_id, port_id, ev, nb_events);
2851 return (fp_ops->dequeue_burst)(port, ev, nb_events, timeout_ticks);
2854#define RTE_EVENT_DEV_MAINT_OP_FLUSH (1 << 0)
2899 const struct rte_event_fp_ops *fp_ops;
2902 fp_ops = &rte_event_fp_ops[dev_id];
2903 port = fp_ops->data[port_id];
2904#ifdef RTE_LIBRTE_EVENTDEV_DEBUG
2905 if (dev_id >= RTE_EVENT_MAX_DEVS ||
2906 port_id >= RTE_EVENT_MAX_PORTS_PER_DEV)
2915 rte_eventdev_trace_maintain(dev_id, port_id, op);
2917 if (fp_ops->maintain != NULL)
2918 fp_ops->maintain(port, op);
2944static inline uint8_t
2947 const struct rte_event_fp_ops *fp_ops;
2950 fp_ops = &rte_event_fp_ops[dev_id];
2951 port = fp_ops->data[port_id];
2953#ifdef RTE_LIBRTE_EVENTDEV_DEBUG
2954 if (dev_id >= RTE_EVENT_MAX_DEVS ||
2955 port_id >= RTE_EVENT_MAX_PORTS_PER_DEV)
2961 if (profile_id >= RTE_EVENT_MAX_PROFILES_PER_PORT)
2964 rte_eventdev_trace_port_profile_switch(dev_id, port_id, profile_id);
2966 return fp_ops->profile_switch(port, profile_id);
2997 const struct rte_event_fp_ops *fp_ops;
3000 fp_ops = &rte_event_fp_ops[dev_id];
3001 port = fp_ops->data[port_id];
3003#ifdef RTE_LIBRTE_EVENTDEV_DEBUG
3004 if (dev_id >= RTE_EVENT_MAX_DEVS || port_id >= RTE_EVENT_MAX_PORTS_PER_DEV)
3010 rte_eventdev_trace_port_preschedule_modify(dev_id, port_id, type);
3012 return fp_ops->preschedule_modify(port, type);
3041 const struct rte_event_fp_ops *fp_ops;
3044 fp_ops = &rte_event_fp_ops[dev_id];
3045 port = fp_ops->data[port_id];
3047#ifdef RTE_LIBRTE_EVENTDEV_DEBUG
3048 if (dev_id >= RTE_EVENT_MAX_DEVS || port_id >= RTE_EVENT_MAX_PORTS_PER_DEV)
3053 rte_eventdev_trace_port_preschedule(dev_id, port_id, type);
3055 fp_ops->preschedule(port, type);
#define __rte_always_inline
struct __rte_aligned(16) rte_event_vector
int rte_event_port_links_get(uint8_t dev_id, uint8_t port_id, uint8_t queues[], uint8_t priorities[])
int rte_event_port_unlinks_in_progress(uint8_t dev_id, uint8_t port_id)
int rte_event_queue_attr_set(uint8_t dev_id, uint8_t queue_id, uint32_t attr_id, uint64_t attr_value)
static __rte_experimental int rte_event_port_preschedule_modify(uint8_t dev_id, uint8_t port_id, enum rte_event_dev_preschedule_type type)
void(* rte_eventdev_port_flush_t)(uint8_t dev_id, struct rte_event event, void *arg)
int rte_event_dequeue_timeout_ticks(uint8_t dev_id, uint64_t ns, uint64_t *timeout_ticks)
int rte_event_port_link(uint8_t dev_id, uint8_t port_id, const uint8_t queues[], const uint8_t priorities[], uint16_t nb_links)
static uint16_t rte_event_enqueue_forward_burst(uint8_t dev_id, uint8_t port_id, const struct rte_event ev[], uint16_t nb_events)
static uint16_t rte_event_dequeue_burst(uint8_t dev_id, uint8_t port_id, struct rte_event ev[], uint16_t nb_events, uint64_t timeout_ticks)
int rte_event_dev_service_id_get(uint8_t dev_id, uint32_t *service_id)
static uint8_t rte_event_port_profile_switch(uint8_t dev_id, uint8_t port_id, uint8_t profile_id)
rte_event_dev_xstats_mode
__rte_experimental int rte_event_port_profile_links_set(uint8_t dev_id, uint8_t port_id, const uint8_t queues[], const uint8_t priorities[], uint16_t nb_links, uint8_t profile_id)
int rte_event_eth_rx_adapter_caps_get(uint8_t dev_id, uint16_t eth_port_id, uint32_t *caps)
int rte_event_queue_setup(uint8_t dev_id, uint8_t queue_id, const struct rte_event_queue_conf *queue_conf)
int rte_event_queue_default_conf_get(uint8_t dev_id, uint8_t queue_id, struct rte_event_queue_conf *queue_conf)
int rte_event_dev_selftest(uint8_t dev_id)
int rte_event_dev_info_get(uint8_t dev_id, struct rte_event_dev_info *dev_info)
int rte_event_dev_stop_flush_callback_register(uint8_t dev_id, rte_eventdev_stop_flush_t callback, void *userdata)
void rte_event_dev_stop(uint8_t dev_id)
uint8_t rte_event_dev_count(void)
rte_event_dev_preschedule_type
@ RTE_EVENT_PRESCHEDULE_ADAPTIVE
@ RTE_EVENT_PRESCHEDULE_NONE
struct rte_mempool * rte_event_vector_pool_create(const char *name, unsigned int n, unsigned int cache_size, uint16_t nb_elem, int socket_id)
int rte_event_crypto_adapter_caps_get(uint8_t dev_id, uint8_t cdev_id, uint32_t *caps)
void rte_event_port_quiesce(uint8_t dev_id, uint8_t port_id, rte_eventdev_port_flush_t release_cb, void *args)
int rte_event_dev_xstats_reset(uint8_t dev_id, enum rte_event_dev_xstats_mode mode, int16_t queue_port_id, const uint64_t ids[], uint32_t nb_ids)
int rte_event_dev_dump(uint8_t dev_id, FILE *f)
int rte_event_timer_adapter_caps_get(uint8_t dev_id, uint32_t *caps)
int rte_event_dev_attr_get(uint8_t dev_id, uint32_t attr_id, uint32_t *attr_value)
int rte_event_dev_get_dev_id(const char *name)
uint64_t rte_event_dev_xstats_by_name_get(uint8_t dev_id, const char *name, uint64_t *id)
int rte_event_dev_xstats_get(uint8_t dev_id, enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id, const uint64_t ids[], uint64_t values[], unsigned int n)
#define RTE_EVENT_DEV_MAINT_OP_FLUSH
static uint16_t rte_event_enqueue_new_burst(uint8_t dev_id, uint8_t port_id, const struct rte_event ev[], uint16_t nb_events)
void(* rte_eventdev_stop_flush_t)(uint8_t dev_id, struct rte_event event, void *arg)
int rte_event_queue_attr_get(uint8_t dev_id, uint8_t queue_id, uint32_t attr_id, uint32_t *attr_value)
__rte_experimental int rte_event_port_profile_links_get(uint8_t dev_id, uint8_t port_id, uint8_t queues[], uint8_t priorities[], uint8_t profile_id)
static int rte_event_maintain(uint8_t dev_id, uint8_t port_id, int op)
int rte_event_port_attr_get(uint8_t dev_id, uint8_t port_id, uint32_t attr_id, uint32_t *attr_value)
int rte_event_dev_start(uint8_t dev_id)
int rte_event_port_default_conf_get(uint8_t dev_id, uint8_t port_id, struct rte_event_port_conf *port_conf)
int rte_event_dev_xstats_names_get(uint8_t dev_id, enum rte_event_dev_xstats_mode mode, uint8_t queue_port_id, struct rte_event_dev_xstats_name *xstats_names, uint64_t *ids, unsigned int size)
int rte_event_port_setup(uint8_t dev_id, uint8_t port_id, const struct rte_event_port_conf *port_conf)
__rte_experimental int rte_event_dma_adapter_caps_get(uint8_t dev_id, uint8_t dmadev_id, uint32_t *caps)
int rte_event_eth_tx_adapter_caps_get(uint8_t dev_id, uint16_t eth_port_id, uint32_t *caps)
int rte_event_port_unlink(uint8_t dev_id, uint8_t port_id, uint8_t queues[], uint16_t nb_unlinks)
__rte_experimental int rte_event_port_profile_unlink(uint8_t dev_id, uint8_t port_id, uint8_t queues[], uint16_t nb_unlinks, uint8_t profile_id)
#define RTE_EVENT_DEV_XSTATS_NAME_SIZE
int rte_event_dev_socket_id(uint8_t dev_id)
int rte_event_dev_configure(uint8_t dev_id, const struct rte_event_dev_config *dev_conf)
int rte_event_dev_close(uint8_t dev_id)
static __rte_experimental void rte_event_port_preschedule(uint8_t dev_id, uint8_t port_id, enum rte_event_dev_preschedule_type type)
static uint16_t rte_event_enqueue_burst(uint8_t dev_id, uint8_t port_id, const struct rte_event ev[], uint16_t nb_events)
uint32_t dequeue_timeout_ns
enum rte_event_dev_preschedule_type preschedule_type
uint8_t nb_single_link_event_port_queues
uint32_t nb_event_port_enqueue_depth
uint32_t nb_event_queue_flows
uint32_t nb_event_port_dequeue_depth
uint8_t max_event_port_links
uint32_t max_event_port_enqueue_depth
uint32_t dequeue_timeout_ns
uint32_t min_dequeue_timeout_ns
uint32_t max_event_queue_flows
uint8_t max_event_port_dequeue_depth
uint8_t max_event_queue_priority_levels
uint8_t max_profiles_per_port
uint8_t max_event_priority_levels
uint32_t max_dequeue_timeout_ns
uint8_t max_single_link_event_port_queue_pairs
int32_t new_event_threshold
uint32_t nb_atomic_order_sequences
struct rte_event_vector * vec
char name[RTE_MEMPOOL_NAMESIZE]