DPDK  2.1.0
rte_ethdev.h
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1 /*-
2  * BSD LICENSE
3  *
4  * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
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12  * notice, this list of conditions and the following disclaimer.
13  * * Redistributions in binary form must reproduce the above copyright
14  * notice, this list of conditions and the following disclaimer in
15  * the documentation and/or other materials provided with the
16  * distribution.
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19  * from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #ifndef _RTE_ETHDEV_H_
35 #define _RTE_ETHDEV_H_
36 
169 #ifdef __cplusplus
170 extern "C" {
171 #endif
172 
173 #include <stdint.h>
174 
175 /* Use this macro to check if LRO API is supported */
176 #define RTE_ETHDEV_HAS_LRO_SUPPORT
177 
178 #include <rte_log.h>
179 #include <rte_interrupts.h>
180 #include <rte_pci.h>
181 #include <rte_dev.h>
182 #include <rte_devargs.h>
183 #include "rte_ether.h"
184 #include "rte_eth_ctrl.h"
185 #include "rte_dev_info.h"
186 
187 struct rte_mbuf;
188 
192 struct rte_eth_stats {
193  uint64_t ipackets;
194  uint64_t opackets;
195  uint64_t ibytes;
196  uint64_t obytes;
197  uint64_t imissed;
199  uint64_t ibadcrc;
201  uint64_t ibadlen;
203  uint64_t ierrors;
204  uint64_t oerrors;
205  uint64_t imcasts;
207  uint64_t rx_nombuf;
208  uint64_t fdirmatch;
210  uint64_t fdirmiss;
212  uint64_t tx_pause_xon;
214  uint64_t rx_pause_xon;
216  uint64_t tx_pause_xoff;
218  uint64_t rx_pause_xoff;
220  uint64_t q_ipackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];
222  uint64_t q_opackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];
224  uint64_t q_ibytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];
226  uint64_t q_obytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];
228  uint64_t q_errors[RTE_ETHDEV_QUEUE_STAT_CNTRS];
230  uint64_t ilbpackets;
232  uint64_t olbpackets;
234  uint64_t ilbbytes;
236  uint64_t olbbytes;
238 };
239 
243 struct rte_eth_link {
244  uint16_t link_speed;
245  uint16_t link_duplex;
246  uint8_t link_status : 1;
247 }__attribute__((aligned(8)));
249 #define ETH_LINK_SPEED_AUTONEG 0
250 #define ETH_LINK_SPEED_10 10
251 #define ETH_LINK_SPEED_100 100
252 #define ETH_LINK_SPEED_1000 1000
253 #define ETH_LINK_SPEED_10000 10000
254 #define ETH_LINK_SPEED_10G 10000
255 #define ETH_LINK_SPEED_20G 20000
256 #define ETH_LINK_SPEED_40G 40000
258 #define ETH_LINK_AUTONEG_DUPLEX 0
259 #define ETH_LINK_HALF_DUPLEX 1
260 #define ETH_LINK_FULL_DUPLEX 2
266 struct rte_eth_thresh {
267  uint8_t pthresh;
268  uint8_t hthresh;
269  uint8_t wthresh;
270 };
271 
275 #define ETH_MQ_RX_RSS_FLAG 0x1
276 #define ETH_MQ_RX_DCB_FLAG 0x2
277 #define ETH_MQ_RX_VMDQ_FLAG 0x4
278 
283 enum rte_eth_rx_mq_mode {
285  ETH_MQ_RX_NONE = 0,
286 
288  ETH_MQ_RX_RSS = ETH_MQ_RX_RSS_FLAG,
290  ETH_MQ_RX_DCB = ETH_MQ_RX_DCB_FLAG,
292  ETH_MQ_RX_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG,
293 
295  ETH_MQ_RX_VMDQ_ONLY = ETH_MQ_RX_VMDQ_FLAG,
297  ETH_MQ_RX_VMDQ_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_VMDQ_FLAG,
299  ETH_MQ_RX_VMDQ_DCB = ETH_MQ_RX_VMDQ_FLAG | ETH_MQ_RX_DCB_FLAG,
301  ETH_MQ_RX_VMDQ_DCB_RSS = ETH_MQ_RX_RSS_FLAG | ETH_MQ_RX_DCB_FLAG |
302  ETH_MQ_RX_VMDQ_FLAG,
303 };
304 
308 #define ETH_RSS ETH_MQ_RX_RSS
309 #define VMDQ_DCB ETH_MQ_RX_VMDQ_DCB
310 #define ETH_DCB_RX ETH_MQ_RX_DCB
311 
316 enum rte_eth_tx_mq_mode {
317  ETH_MQ_TX_NONE = 0,
318  ETH_MQ_TX_DCB,
319  ETH_MQ_TX_VMDQ_DCB,
320  ETH_MQ_TX_VMDQ_ONLY,
321 };
322 
326 #define ETH_DCB_NONE ETH_MQ_TX_NONE
327 #define ETH_VMDQ_DCB_TX ETH_MQ_TX_VMDQ_DCB
328 #define ETH_DCB_TX ETH_MQ_TX_DCB
329 
333 struct rte_eth_rxmode {
335  enum rte_eth_rx_mq_mode mq_mode;
336  uint32_t max_rx_pkt_len;
337  uint16_t split_hdr_size;
338  uint16_t header_split : 1,
339  hw_ip_checksum : 1,
340  hw_vlan_filter : 1,
341  hw_vlan_strip : 1,
342  hw_vlan_extend : 1,
343  jumbo_frame : 1,
344  hw_strip_crc : 1,
345  enable_scatter : 1,
346  enable_lro : 1;
347 };
348 
366 struct rte_eth_rss_conf {
367  uint8_t *rss_key;
368  uint8_t rss_key_len;
369  uint64_t rss_hf;
370 };
371 
372 /*
373  * The RSS offload types are defined based on flow types which are defined
374  * in rte_eth_ctrl.h. Different NIC hardwares may support different RSS offload
375  * types. The supported flow types or RSS offload types can be queried by
376  * rte_eth_dev_info_get().
377  */
378 #define ETH_RSS_IPV4 (1ULL << RTE_ETH_FLOW_IPV4)
379 #define ETH_RSS_FRAG_IPV4 (1ULL << RTE_ETH_FLOW_FRAG_IPV4)
380 #define ETH_RSS_NONFRAG_IPV4_TCP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP)
381 #define ETH_RSS_NONFRAG_IPV4_UDP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP)
382 #define ETH_RSS_NONFRAG_IPV4_SCTP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP)
383 #define ETH_RSS_NONFRAG_IPV4_OTHER (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER)
384 #define ETH_RSS_IPV6 (1ULL << RTE_ETH_FLOW_IPV6)
385 #define ETH_RSS_FRAG_IPV6 (1ULL << RTE_ETH_FLOW_FRAG_IPV6)
386 #define ETH_RSS_NONFRAG_IPV6_TCP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP)
387 #define ETH_RSS_NONFRAG_IPV6_UDP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP)
388 #define ETH_RSS_NONFRAG_IPV6_SCTP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP)
389 #define ETH_RSS_NONFRAG_IPV6_OTHER (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER)
390 #define ETH_RSS_L2_PAYLOAD (1ULL << RTE_ETH_FLOW_L2_PAYLOAD)
391 #define ETH_RSS_IPV6_EX (1ULL << RTE_ETH_FLOW_IPV6_EX)
392 #define ETH_RSS_IPV6_TCP_EX (1ULL << RTE_ETH_FLOW_IPV6_TCP_EX)
393 #define ETH_RSS_IPV6_UDP_EX (1ULL << RTE_ETH_FLOW_IPV6_UDP_EX)
394 
395 #define ETH_RSS_IP ( \
396  ETH_RSS_IPV4 | \
397  ETH_RSS_FRAG_IPV4 | \
398  ETH_RSS_NONFRAG_IPV4_OTHER | \
399  ETH_RSS_IPV6 | \
400  ETH_RSS_FRAG_IPV6 | \
401  ETH_RSS_NONFRAG_IPV6_OTHER | \
402  ETH_RSS_IPV6_EX)
403 
404 #define ETH_RSS_UDP ( \
405  ETH_RSS_NONFRAG_IPV4_UDP | \
406  ETH_RSS_NONFRAG_IPV6_UDP | \
407  ETH_RSS_IPV6_UDP_EX)
408 
409 #define ETH_RSS_TCP ( \
410  ETH_RSS_NONFRAG_IPV4_TCP | \
411  ETH_RSS_NONFRAG_IPV6_TCP | \
412  ETH_RSS_IPV6_TCP_EX)
413 
414 #define ETH_RSS_SCTP ( \
415  ETH_RSS_NONFRAG_IPV4_SCTP | \
416  ETH_RSS_NONFRAG_IPV6_SCTP)
417 
419 #define ETH_RSS_PROTO_MASK ( \
420  ETH_RSS_IPV4 | \
421  ETH_RSS_FRAG_IPV4 | \
422  ETH_RSS_NONFRAG_IPV4_TCP | \
423  ETH_RSS_NONFRAG_IPV4_UDP | \
424  ETH_RSS_NONFRAG_IPV4_SCTP | \
425  ETH_RSS_NONFRAG_IPV4_OTHER | \
426  ETH_RSS_IPV6 | \
427  ETH_RSS_FRAG_IPV6 | \
428  ETH_RSS_NONFRAG_IPV6_TCP | \
429  ETH_RSS_NONFRAG_IPV6_UDP | \
430  ETH_RSS_NONFRAG_IPV6_SCTP | \
431  ETH_RSS_NONFRAG_IPV6_OTHER | \
432  ETH_RSS_L2_PAYLOAD | \
433  ETH_RSS_IPV6_EX | \
434  ETH_RSS_IPV6_TCP_EX | \
435  ETH_RSS_IPV6_UDP_EX)
436 
437 /*
438  * Definitions used for redirection table entry size.
439  * Some RSS RETA sizes may not be supported by some drivers, check the
440  * documentation or the description of relevant functions for more details.
441  */
442 #define ETH_RSS_RETA_SIZE_64 64
443 #define ETH_RSS_RETA_SIZE_128 128
444 #define ETH_RSS_RETA_SIZE_512 512
445 #define RTE_RETA_GROUP_SIZE 64
446 
447 /* Definitions used for VMDQ and DCB functionality */
448 #define ETH_VMDQ_MAX_VLAN_FILTERS 64
449 #define ETH_DCB_NUM_USER_PRIORITIES 8
450 #define ETH_VMDQ_DCB_NUM_QUEUES 128
451 #define ETH_DCB_NUM_QUEUES 128
453 /* DCB capability defines */
454 #define ETH_DCB_PG_SUPPORT 0x00000001
455 #define ETH_DCB_PFC_SUPPORT 0x00000002
457 /* Definitions used for VLAN Offload functionality */
458 #define ETH_VLAN_STRIP_OFFLOAD 0x0001
459 #define ETH_VLAN_FILTER_OFFLOAD 0x0002
460 #define ETH_VLAN_EXTEND_OFFLOAD 0x0004
462 /* Definitions used for mask VLAN setting */
463 #define ETH_VLAN_STRIP_MASK 0x0001
464 #define ETH_VLAN_FILTER_MASK 0x0002
465 #define ETH_VLAN_EXTEND_MASK 0x0004
466 #define ETH_VLAN_ID_MAX 0x0FFF
468 /* Definitions used for receive MAC address */
469 #define ETH_NUM_RECEIVE_MAC_ADDR 128
471 /* Definitions used for unicast hash */
472 #define ETH_VMDQ_NUM_UC_HASH_ARRAY 128
474 /* Definitions used for VMDQ pool rx mode setting */
475 #define ETH_VMDQ_ACCEPT_UNTAG 0x0001
476 #define ETH_VMDQ_ACCEPT_HASH_MC 0x0002
477 #define ETH_VMDQ_ACCEPT_HASH_UC 0x0004
478 #define ETH_VMDQ_ACCEPT_BROADCAST 0x0008
479 #define ETH_VMDQ_ACCEPT_MULTICAST 0x0010
482 #define ETH_MIRROR_MAX_VLANS 64
483 
484 #define ETH_MIRROR_VIRTUAL_POOL_UP 0x01
485 #define ETH_MIRROR_UPLINK_PORT 0x02
486 #define ETH_MIRROR_DOWNLINK_PORT 0x04
487 #define ETH_MIRROR_VLAN 0x08
488 #define ETH_MIRROR_VIRTUAL_POOL_DOWN 0x10
493 struct rte_eth_vlan_mirror {
494  uint64_t vlan_mask;
496  uint16_t vlan_id[ETH_MIRROR_MAX_VLANS];
497 };
498 
502 struct rte_eth_mirror_conf {
503  uint8_t rule_type;
504  uint8_t dst_pool;
505  uint64_t pool_mask;
507  struct rte_eth_vlan_mirror vlan;
508 };
509 
516 struct rte_eth_rss_reta_entry64 {
517  uint64_t mask;
519  uint8_t reta[RTE_RETA_GROUP_SIZE];
521 };
522 
527 enum rte_eth_nb_tcs {
528  ETH_4_TCS = 4,
529  ETH_8_TCS = 8
530 };
531 
536 enum rte_eth_nb_pools {
537  ETH_8_POOLS = 8,
538  ETH_16_POOLS = 16,
539  ETH_32_POOLS = 32,
540  ETH_64_POOLS = 64
541 };
542 
543 /* This structure may be extended in future. */
544 struct rte_eth_dcb_rx_conf {
545  enum rte_eth_nb_tcs nb_tcs;
546  uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
548 };
549 
550 struct rte_eth_vmdq_dcb_tx_conf {
551  enum rte_eth_nb_pools nb_queue_pools;
552  uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
554 };
555 
556 struct rte_eth_dcb_tx_conf {
557  enum rte_eth_nb_tcs nb_tcs;
558  uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
560 };
561 
562 struct rte_eth_vmdq_tx_conf {
563  enum rte_eth_nb_pools nb_queue_pools;
564 };
565 
577 struct rte_eth_vmdq_dcb_conf {
578  enum rte_eth_nb_pools nb_queue_pools;
579  uint8_t enable_default_pool;
580  uint8_t default_pool;
581  uint8_t nb_pool_maps;
582  struct {
583  uint16_t vlan_id;
584  uint64_t pools;
585  } pool_map[ETH_VMDQ_MAX_VLAN_FILTERS];
586  uint8_t dcb_queue[ETH_DCB_NUM_USER_PRIORITIES];
588 };
589 
590 struct rte_eth_vmdq_rx_conf {
591  enum rte_eth_nb_pools nb_queue_pools;
592  uint8_t enable_default_pool;
593  uint8_t default_pool;
594  uint8_t enable_loop_back;
595  uint8_t nb_pool_maps;
596  uint32_t rx_mode;
597  struct {
598  uint16_t vlan_id;
599  uint64_t pools;
600  } pool_map[ETH_VMDQ_MAX_VLAN_FILTERS];
601 };
602 
606 struct rte_eth_txmode {
607  enum rte_eth_tx_mq_mode mq_mode;
609  /* For i40e specifically */
610  uint16_t pvid;
611  uint8_t hw_vlan_reject_tagged : 1,
613  hw_vlan_reject_untagged : 1,
615  hw_vlan_insert_pvid : 1;
617 };
618 
622 struct rte_eth_rxconf {
623  struct rte_eth_thresh rx_thresh;
624  uint16_t rx_free_thresh;
625  uint8_t rx_drop_en;
626  uint8_t rx_deferred_start;
627 };
628 
629 #define ETH_TXQ_FLAGS_NOMULTSEGS 0x0001
630 #define ETH_TXQ_FLAGS_NOREFCOUNT 0x0002
631 #define ETH_TXQ_FLAGS_NOMULTMEMP 0x0004
632 #define ETH_TXQ_FLAGS_NOVLANOFFL 0x0100
633 #define ETH_TXQ_FLAGS_NOXSUMSCTP 0x0200
634 #define ETH_TXQ_FLAGS_NOXSUMUDP 0x0400
635 #define ETH_TXQ_FLAGS_NOXSUMTCP 0x0800
636 #define ETH_TXQ_FLAGS_NOOFFLOADS \
637  (ETH_TXQ_FLAGS_NOVLANOFFL | ETH_TXQ_FLAGS_NOXSUMSCTP | \
638  ETH_TXQ_FLAGS_NOXSUMUDP | ETH_TXQ_FLAGS_NOXSUMTCP)
639 #define ETH_TXQ_FLAGS_NOXSUMS \
640  (ETH_TXQ_FLAGS_NOXSUMSCTP | ETH_TXQ_FLAGS_NOXSUMUDP | \
641  ETH_TXQ_FLAGS_NOXSUMTCP)
642 
645 struct rte_eth_txconf {
646  struct rte_eth_thresh tx_thresh;
647  uint16_t tx_rs_thresh;
648  uint16_t tx_free_thresh;
651  uint32_t txq_flags;
652  uint8_t tx_deferred_start;
653 };
654 
658 enum rte_eth_fc_mode {
659  RTE_FC_NONE = 0,
660  RTE_FC_RX_PAUSE,
661  RTE_FC_TX_PAUSE,
662  RTE_FC_FULL
663 };
664 
670 struct rte_eth_fc_conf {
671  uint32_t high_water;
672  uint32_t low_water;
673  uint16_t pause_time;
674  uint16_t send_xon;
675  enum rte_eth_fc_mode mode;
676  uint8_t mac_ctrl_frame_fwd;
677  uint8_t autoneg;
678 };
679 
685 struct rte_eth_pfc_conf {
686  struct rte_eth_fc_conf fc;
687  uint8_t priority;
688 };
689 
694 enum rte_fdir_pballoc_type {
695  RTE_FDIR_PBALLOC_64K = 0,
696  RTE_FDIR_PBALLOC_128K,
697  RTE_FDIR_PBALLOC_256K,
698 };
699 
703 enum rte_fdir_status_mode {
704  RTE_FDIR_NO_REPORT_STATUS = 0,
705  RTE_FDIR_REPORT_STATUS,
706  RTE_FDIR_REPORT_STATUS_ALWAYS,
707 };
708 
715 struct rte_fdir_conf {
716  enum rte_fdir_mode mode;
717  enum rte_fdir_pballoc_type pballoc;
718  enum rte_fdir_status_mode status;
720  uint8_t drop_queue;
721  struct rte_eth_fdir_masks mask;
722  struct rte_eth_fdir_flex_conf flex_conf;
724 };
725 
729 struct rte_eth_udp_tunnel {
730  uint16_t udp_port;
731  uint8_t prot_type;
732 };
733 
737 enum rte_l4type {
738  RTE_FDIR_L4TYPE_NONE = 0,
739  RTE_FDIR_L4TYPE_UDP,
740  RTE_FDIR_L4TYPE_TCP,
741  RTE_FDIR_L4TYPE_SCTP,
742 };
743 
747 enum rte_iptype {
748  RTE_FDIR_IPTYPE_IPV4 = 0,
749  RTE_FDIR_IPTYPE_IPV6 ,
750 };
751 
755 struct rte_fdir_filter {
756  uint16_t flex_bytes;
757  uint16_t vlan_id;
758  uint16_t port_src;
759  uint16_t port_dst;
760  union {
761  uint32_t ipv4_addr;
762  uint32_t ipv6_addr[4];
763  } ip_src;
764  union {
765  uint32_t ipv4_addr;
766  uint32_t ipv6_addr[4];
767  } ip_dst;
768  enum rte_l4type l4type;
769  enum rte_iptype iptype;
770 };
771 
778 struct rte_fdir_masks {
781  uint8_t only_ip_flow;
783  uint8_t vlan_id;
785  uint8_t vlan_prio;
787  uint8_t flexbytes;
789  uint8_t set_ipv6_mask;
792  uint8_t comp_ipv6_dst;
796  uint32_t dst_ipv4_mask;
800  uint32_t src_ipv4_mask;
804  uint16_t dst_ipv6_mask;
808  uint16_t src_ipv6_mask;
812  uint16_t src_port_mask;
816  uint16_t dst_port_mask;
817 };
818 
822 struct rte_eth_fdir {
824  uint16_t collision;
826  uint16_t free;
829  uint16_t maxhash;
831  uint8_t maxlen;
833  uint64_t add;
835  uint64_t remove;
837  uint64_t f_add;
839  uint64_t f_remove;
840 };
841 
845 struct rte_intr_conf {
847  uint16_t lsc;
848 #ifdef RTE_NEXT_ABI
849 
850  uint16_t rxq;
851 #endif
852 };
853 
859 struct rte_eth_conf {
860  uint16_t link_speed;
862  uint16_t link_duplex;
864  struct rte_eth_rxmode rxmode;
865  struct rte_eth_txmode txmode;
866  uint32_t lpbk_mode;
871  struct {
872  struct rte_eth_rss_conf rss_conf;
873  struct rte_eth_vmdq_dcb_conf vmdq_dcb_conf;
875  struct rte_eth_dcb_rx_conf dcb_rx_conf;
877  struct rte_eth_vmdq_rx_conf vmdq_rx_conf;
879  } rx_adv_conf;
880  union {
881  struct rte_eth_vmdq_dcb_tx_conf vmdq_dcb_tx_conf;
883  struct rte_eth_dcb_tx_conf dcb_tx_conf;
885  struct rte_eth_vmdq_tx_conf vmdq_tx_conf;
887  } tx_adv_conf;
890  uint32_t dcb_capability_en;
891  struct rte_fdir_conf fdir_conf;
892  struct rte_intr_conf intr_conf;
893 };
894 
904 #define DEV_RX_OFFLOAD_VLAN_STRIP 0x00000001
905 #define DEV_RX_OFFLOAD_IPV4_CKSUM 0x00000002
906 #define DEV_RX_OFFLOAD_UDP_CKSUM 0x00000004
907 #define DEV_RX_OFFLOAD_TCP_CKSUM 0x00000008
908 #define DEV_RX_OFFLOAD_TCP_LRO 0x00000010
909 #define DEV_RX_OFFLOAD_QINQ_STRIP 0x00000020
910 
914 #define DEV_TX_OFFLOAD_VLAN_INSERT 0x00000001
915 #define DEV_TX_OFFLOAD_IPV4_CKSUM 0x00000002
916 #define DEV_TX_OFFLOAD_UDP_CKSUM 0x00000004
917 #define DEV_TX_OFFLOAD_TCP_CKSUM 0x00000008
918 #define DEV_TX_OFFLOAD_SCTP_CKSUM 0x00000010
919 #define DEV_TX_OFFLOAD_TCP_TSO 0x00000020
920 #define DEV_TX_OFFLOAD_UDP_TSO 0x00000040
921 #define DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM 0x00000080
922 #define DEV_TX_OFFLOAD_QINQ_INSERT 0x00000100
923 
924 struct rte_eth_dev_info {
925  struct rte_pci_device *pci_dev;
926  const char *driver_name;
927  unsigned int if_index;
929  uint32_t min_rx_bufsize;
930  uint32_t max_rx_pktlen;
931  uint16_t max_rx_queues;
932  uint16_t max_tx_queues;
933  uint32_t max_mac_addrs;
934  uint32_t max_hash_mac_addrs;
936  uint16_t max_vfs;
937  uint16_t max_vmdq_pools;
938  uint32_t rx_offload_capa;
939  uint32_t tx_offload_capa;
940  uint16_t reta_size;
942  uint8_t hash_key_size;
944  uint64_t flow_type_rss_offloads;
945  struct rte_eth_rxconf default_rxconf;
946  struct rte_eth_txconf default_txconf;
947  uint16_t vmdq_queue_base;
948  uint16_t vmdq_queue_num;
949  uint16_t vmdq_pool_base;
950 };
951 
953 #define RTE_ETH_XSTATS_NAME_SIZE 64
954 
962 struct rte_eth_xstats {
963  char name[RTE_ETH_XSTATS_NAME_SIZE];
964  uint64_t value;
965 };
966 
967 struct rte_eth_dev;
968 
969 struct rte_eth_dev_callback;
971 TAILQ_HEAD(rte_eth_dev_cb_list, rte_eth_dev_callback);
972 
973 /*
974  * Definitions of all functions exported by an Ethernet driver through the
975  * the generic structure of type *eth_dev_ops* supplied in the *rte_eth_dev*
976  * structure associated with an Ethernet device.
977  */
978 
979 typedef int (*eth_dev_configure_t)(struct rte_eth_dev *dev);
982 typedef int (*eth_dev_start_t)(struct rte_eth_dev *dev);
985 typedef void (*eth_dev_stop_t)(struct rte_eth_dev *dev);
988 typedef int (*eth_dev_set_link_up_t)(struct rte_eth_dev *dev);
991 typedef int (*eth_dev_set_link_down_t)(struct rte_eth_dev *dev);
994 typedef void (*eth_dev_close_t)(struct rte_eth_dev *dev);
997 typedef void (*eth_promiscuous_enable_t)(struct rte_eth_dev *dev);
1000 typedef void (*eth_promiscuous_disable_t)(struct rte_eth_dev *dev);
1003 typedef void (*eth_allmulticast_enable_t)(struct rte_eth_dev *dev);
1006 typedef void (*eth_allmulticast_disable_t)(struct rte_eth_dev *dev);
1009 typedef int (*eth_link_update_t)(struct rte_eth_dev *dev,
1010  int wait_to_complete);
1013 typedef void (*eth_stats_get_t)(struct rte_eth_dev *dev,
1014  struct rte_eth_stats *igb_stats);
1017 typedef void (*eth_stats_reset_t)(struct rte_eth_dev *dev);
1020 typedef int (*eth_xstats_get_t)(struct rte_eth_dev *dev,
1021  struct rte_eth_xstats *stats, unsigned n);
1024 typedef void (*eth_xstats_reset_t)(struct rte_eth_dev *dev);
1027 typedef int (*eth_queue_stats_mapping_set_t)(struct rte_eth_dev *dev,
1028  uint16_t queue_id,
1029  uint8_t stat_idx,
1030  uint8_t is_rx);
1033 typedef void (*eth_dev_infos_get_t)(struct rte_eth_dev *dev,
1034  struct rte_eth_dev_info *dev_info);
1037 typedef int (*eth_queue_start_t)(struct rte_eth_dev *dev,
1038  uint16_t queue_id);
1041 typedef int (*eth_queue_stop_t)(struct rte_eth_dev *dev,
1042  uint16_t queue_id);
1045 typedef int (*eth_rx_queue_setup_t)(struct rte_eth_dev *dev,
1046  uint16_t rx_queue_id,
1047  uint16_t nb_rx_desc,
1048  unsigned int socket_id,
1049  const struct rte_eth_rxconf *rx_conf,
1050  struct rte_mempool *mb_pool);
1053 typedef int (*eth_tx_queue_setup_t)(struct rte_eth_dev *dev,
1054  uint16_t tx_queue_id,
1055  uint16_t nb_tx_desc,
1056  unsigned int socket_id,
1057  const struct rte_eth_txconf *tx_conf);
1060 typedef int (*eth_rx_enable_intr_t)(struct rte_eth_dev *dev,
1061  uint16_t rx_queue_id);
1064 typedef int (*eth_rx_disable_intr_t)(struct rte_eth_dev *dev,
1065  uint16_t rx_queue_id);
1068 typedef void (*eth_queue_release_t)(void *queue);
1071 typedef uint32_t (*eth_rx_queue_count_t)(struct rte_eth_dev *dev,
1072  uint16_t rx_queue_id);
1075 typedef int (*eth_rx_descriptor_done_t)(void *rxq, uint16_t offset);
1078 typedef int (*mtu_set_t)(struct rte_eth_dev *dev, uint16_t mtu);
1081 typedef int (*vlan_filter_set_t)(struct rte_eth_dev *dev,
1082  uint16_t vlan_id,
1083  int on);
1086 typedef void (*vlan_tpid_set_t)(struct rte_eth_dev *dev,
1087  uint16_t tpid);
1090 typedef void (*vlan_offload_set_t)(struct rte_eth_dev *dev, int mask);
1093 typedef int (*vlan_pvid_set_t)(struct rte_eth_dev *dev,
1094  uint16_t vlan_id,
1095  int on);
1098 typedef void (*vlan_strip_queue_set_t)(struct rte_eth_dev *dev,
1099  uint16_t rx_queue_id,
1100  int on);
1103 typedef uint16_t (*eth_rx_burst_t)(void *rxq,
1104  struct rte_mbuf **rx_pkts,
1105  uint16_t nb_pkts);
1108 typedef uint16_t (*eth_tx_burst_t)(void *txq,
1109  struct rte_mbuf **tx_pkts,
1110  uint16_t nb_pkts);
1113 typedef int (*fdir_add_signature_filter_t)(struct rte_eth_dev *dev,
1114  struct rte_fdir_filter *fdir_ftr,
1115  uint8_t rx_queue);
1118 typedef int (*fdir_update_signature_filter_t)(struct rte_eth_dev *dev,
1119  struct rte_fdir_filter *fdir_ftr,
1120  uint8_t rx_queue);
1123 typedef int (*fdir_remove_signature_filter_t)(struct rte_eth_dev *dev,
1124  struct rte_fdir_filter *fdir_ftr);
1127 typedef void (*fdir_infos_get_t)(struct rte_eth_dev *dev,
1128  struct rte_eth_fdir *fdir);
1131 typedef int (*fdir_add_perfect_filter_t)(struct rte_eth_dev *dev,
1132  struct rte_fdir_filter *fdir_ftr,
1133  uint16_t soft_id, uint8_t rx_queue,
1134  uint8_t drop);
1137 typedef int (*fdir_update_perfect_filter_t)(struct rte_eth_dev *dev,
1138  struct rte_fdir_filter *fdir_ftr,
1139  uint16_t soft_id, uint8_t rx_queue,
1140  uint8_t drop);
1143 typedef int (*fdir_remove_perfect_filter_t)(struct rte_eth_dev *dev,
1144  struct rte_fdir_filter *fdir_ftr,
1145  uint16_t soft_id);
1148 typedef int (*fdir_set_masks_t)(struct rte_eth_dev *dev,
1149  struct rte_fdir_masks *fdir_masks);
1152 typedef int (*flow_ctrl_get_t)(struct rte_eth_dev *dev,
1153  struct rte_eth_fc_conf *fc_conf);
1156 typedef int (*flow_ctrl_set_t)(struct rte_eth_dev *dev,
1157  struct rte_eth_fc_conf *fc_conf);
1160 typedef int (*priority_flow_ctrl_set_t)(struct rte_eth_dev *dev,
1161  struct rte_eth_pfc_conf *pfc_conf);
1164 typedef int (*reta_update_t)(struct rte_eth_dev *dev,
1165  struct rte_eth_rss_reta_entry64 *reta_conf,
1166  uint16_t reta_size);
1169 typedef int (*reta_query_t)(struct rte_eth_dev *dev,
1170  struct rte_eth_rss_reta_entry64 *reta_conf,
1171  uint16_t reta_size);
1174 typedef int (*rss_hash_update_t)(struct rte_eth_dev *dev,
1175  struct rte_eth_rss_conf *rss_conf);
1178 typedef int (*rss_hash_conf_get_t)(struct rte_eth_dev *dev,
1179  struct rte_eth_rss_conf *rss_conf);
1182 typedef int (*eth_dev_led_on_t)(struct rte_eth_dev *dev);
1185 typedef int (*eth_dev_led_off_t)(struct rte_eth_dev *dev);
1188 typedef void (*eth_mac_addr_remove_t)(struct rte_eth_dev *dev, uint32_t index);
1191 typedef void (*eth_mac_addr_add_t)(struct rte_eth_dev *dev,
1192  struct ether_addr *mac_addr,
1193  uint32_t index,
1194  uint32_t vmdq);
1197 typedef void (*eth_mac_addr_set_t)(struct rte_eth_dev *dev,
1198  struct ether_addr *mac_addr);
1201 typedef int (*eth_uc_hash_table_set_t)(struct rte_eth_dev *dev,
1202  struct ether_addr *mac_addr,
1203  uint8_t on);
1206 typedef int (*eth_uc_all_hash_table_set_t)(struct rte_eth_dev *dev,
1207  uint8_t on);
1210 typedef int (*eth_set_vf_rx_mode_t)(struct rte_eth_dev *dev,
1211  uint16_t vf,
1212  uint16_t rx_mode,
1213  uint8_t on);
1216 typedef int (*eth_set_vf_rx_t)(struct rte_eth_dev *dev,
1217  uint16_t vf,
1218  uint8_t on);
1221 typedef int (*eth_set_vf_tx_t)(struct rte_eth_dev *dev,
1222  uint16_t vf,
1223  uint8_t on);
1226 typedef int (*eth_set_vf_vlan_filter_t)(struct rte_eth_dev *dev,
1227  uint16_t vlan,
1228  uint64_t vf_mask,
1229  uint8_t vlan_on);
1232 typedef int (*eth_set_queue_rate_limit_t)(struct rte_eth_dev *dev,
1233  uint16_t queue_idx,
1234  uint16_t tx_rate);
1237 typedef int (*eth_set_vf_rate_limit_t)(struct rte_eth_dev *dev,
1238  uint16_t vf,
1239  uint16_t tx_rate,
1240  uint64_t q_msk);
1243 typedef int (*eth_mirror_rule_set_t)(struct rte_eth_dev *dev,
1244  struct rte_eth_mirror_conf *mirror_conf,
1245  uint8_t rule_id,
1246  uint8_t on);
1249 typedef int (*eth_mirror_rule_reset_t)(struct rte_eth_dev *dev,
1250  uint8_t rule_id);
1253 typedef int (*eth_udp_tunnel_add_t)(struct rte_eth_dev *dev,
1254  struct rte_eth_udp_tunnel *tunnel_udp);
1257 typedef int (*eth_udp_tunnel_del_t)(struct rte_eth_dev *dev,
1258  struct rte_eth_udp_tunnel *tunnel_udp);
1261 typedef int (*eth_set_mc_addr_list_t)(struct rte_eth_dev *dev,
1262  struct ether_addr *mc_addr_set,
1263  uint32_t nb_mc_addr);
1266 typedef int (*eth_timesync_enable_t)(struct rte_eth_dev *dev);
1269 typedef int (*eth_timesync_disable_t)(struct rte_eth_dev *dev);
1272 typedef int (*eth_timesync_read_rx_timestamp_t)(struct rte_eth_dev *dev,
1273  struct timespec *timestamp,
1274  uint32_t flags);
1277 typedef int (*eth_timesync_read_tx_timestamp_t)(struct rte_eth_dev *dev,
1278  struct timespec *timestamp);
1281 typedef int (*eth_get_reg_length_t)(struct rte_eth_dev *dev);
1284 typedef int (*eth_get_reg_t)(struct rte_eth_dev *dev,
1285  struct rte_dev_reg_info *info);
1288 typedef int (*eth_get_eeprom_length_t)(struct rte_eth_dev *dev);
1291 typedef int (*eth_get_eeprom_t)(struct rte_eth_dev *dev,
1292  struct rte_dev_eeprom_info *info);
1295 typedef int (*eth_set_eeprom_t)(struct rte_eth_dev *dev,
1296  struct rte_dev_eeprom_info *info);
1299 #ifdef RTE_NIC_BYPASS
1300 
1301 enum {
1302  RTE_BYPASS_MODE_NONE,
1303  RTE_BYPASS_MODE_NORMAL,
1304  RTE_BYPASS_MODE_BYPASS,
1305  RTE_BYPASS_MODE_ISOLATE,
1306  RTE_BYPASS_MODE_NUM,
1307 };
1308 
1309 #define RTE_BYPASS_MODE_VALID(x) \
1310  ((x) > RTE_BYPASS_MODE_NONE && (x) < RTE_BYPASS_MODE_NUM)
1311 
1312 enum {
1313  RTE_BYPASS_EVENT_NONE,
1314  RTE_BYPASS_EVENT_START,
1315  RTE_BYPASS_EVENT_OS_ON = RTE_BYPASS_EVENT_START,
1316  RTE_BYPASS_EVENT_POWER_ON,
1317  RTE_BYPASS_EVENT_OS_OFF,
1318  RTE_BYPASS_EVENT_POWER_OFF,
1319  RTE_BYPASS_EVENT_TIMEOUT,
1320  RTE_BYPASS_EVENT_NUM
1321 };
1322 
1323 #define RTE_BYPASS_EVENT_VALID(x) \
1324  ((x) > RTE_BYPASS_EVENT_NONE && (x) < RTE_BYPASS_MODE_NUM)
1325 
1326 enum {
1327  RTE_BYPASS_TMT_OFF, /* timeout disabled. */
1328  RTE_BYPASS_TMT_1_5_SEC, /* timeout for 1.5 seconds */
1329  RTE_BYPASS_TMT_2_SEC, /* timeout for 2 seconds */
1330  RTE_BYPASS_TMT_3_SEC, /* timeout for 3 seconds */
1331  RTE_BYPASS_TMT_4_SEC, /* timeout for 4 seconds */
1332  RTE_BYPASS_TMT_8_SEC, /* timeout for 8 seconds */
1333  RTE_BYPASS_TMT_16_SEC, /* timeout for 16 seconds */
1334  RTE_BYPASS_TMT_32_SEC, /* timeout for 32 seconds */
1335  RTE_BYPASS_TMT_NUM
1336 };
1337 
1338 #define RTE_BYPASS_TMT_VALID(x) \
1339  ((x) == RTE_BYPASS_TMT_OFF || \
1340  ((x) > RTE_BYPASS_TMT_OFF && (x) < RTE_BYPASS_TMT_NUM))
1341 
1342 typedef void (*bypass_init_t)(struct rte_eth_dev *dev);
1343 typedef int32_t (*bypass_state_set_t)(struct rte_eth_dev *dev, uint32_t *new_state);
1344 typedef int32_t (*bypass_state_show_t)(struct rte_eth_dev *dev, uint32_t *state);
1345 typedef int32_t (*bypass_event_set_t)(struct rte_eth_dev *dev, uint32_t state, uint32_t event);
1346 typedef int32_t (*bypass_event_show_t)(struct rte_eth_dev *dev, uint32_t event_shift, uint32_t *event);
1347 typedef int32_t (*bypass_wd_timeout_set_t)(struct rte_eth_dev *dev, uint32_t timeout);
1348 typedef int32_t (*bypass_wd_timeout_show_t)(struct rte_eth_dev *dev, uint32_t *wd_timeout);
1349 typedef int32_t (*bypass_ver_show_t)(struct rte_eth_dev *dev, uint32_t *ver);
1350 typedef int32_t (*bypass_wd_reset_t)(struct rte_eth_dev *dev);
1351 #endif
1352 
1353 typedef int (*eth_filter_ctrl_t)(struct rte_eth_dev *dev,
1354  enum rte_filter_type filter_type,
1355  enum rte_filter_op filter_op,
1356  void *arg);
1362 struct eth_dev_ops {
1363  eth_dev_configure_t dev_configure;
1364  eth_dev_start_t dev_start;
1365  eth_dev_stop_t dev_stop;
1366  eth_dev_set_link_up_t dev_set_link_up;
1367  eth_dev_set_link_down_t dev_set_link_down;
1368  eth_dev_close_t dev_close;
1369  eth_promiscuous_enable_t promiscuous_enable;
1370  eth_promiscuous_disable_t promiscuous_disable;
1371  eth_allmulticast_enable_t allmulticast_enable;
1372  eth_allmulticast_disable_t allmulticast_disable;
1373  eth_link_update_t link_update;
1374  eth_stats_get_t stats_get;
1375  eth_stats_reset_t stats_reset;
1376  eth_xstats_get_t xstats_get;
1377  eth_xstats_reset_t xstats_reset;
1378  eth_queue_stats_mapping_set_t queue_stats_mapping_set;
1380  eth_dev_infos_get_t dev_infos_get;
1381  mtu_set_t mtu_set;
1382  vlan_filter_set_t vlan_filter_set;
1383  vlan_tpid_set_t vlan_tpid_set;
1384  vlan_strip_queue_set_t vlan_strip_queue_set;
1385  vlan_offload_set_t vlan_offload_set;
1386  vlan_pvid_set_t vlan_pvid_set;
1387  eth_queue_start_t rx_queue_start;
1388  eth_queue_stop_t rx_queue_stop;
1389  eth_queue_start_t tx_queue_start;
1390  eth_queue_stop_t tx_queue_stop;
1391  eth_rx_queue_setup_t rx_queue_setup;
1392  eth_queue_release_t rx_queue_release;
1393  eth_rx_queue_count_t rx_queue_count;
1394  eth_rx_descriptor_done_t rx_descriptor_done;
1395 #ifdef RTE_NEXT_ABI
1396 
1397  eth_rx_enable_intr_t rx_queue_intr_enable;
1399  eth_rx_disable_intr_t rx_queue_intr_disable;
1400 #endif
1401  eth_tx_queue_setup_t tx_queue_setup;
1402  eth_queue_release_t tx_queue_release;
1403  eth_dev_led_on_t dev_led_on;
1404  eth_dev_led_off_t dev_led_off;
1405  flow_ctrl_get_t flow_ctrl_get;
1406  flow_ctrl_set_t flow_ctrl_set;
1407  priority_flow_ctrl_set_t priority_flow_ctrl_set;
1408  eth_mac_addr_remove_t mac_addr_remove;
1409  eth_mac_addr_add_t mac_addr_add;
1410  eth_mac_addr_set_t mac_addr_set;
1411  eth_uc_hash_table_set_t uc_hash_table_set;
1412  eth_uc_all_hash_table_set_t uc_all_hash_table_set;
1413  eth_mirror_rule_set_t mirror_rule_set;
1414  eth_mirror_rule_reset_t mirror_rule_reset;
1415  eth_set_vf_rx_mode_t set_vf_rx_mode;
1416  eth_set_vf_rx_t set_vf_rx;
1417  eth_set_vf_tx_t set_vf_tx;
1418  eth_set_vf_vlan_filter_t set_vf_vlan_filter;
1419  eth_udp_tunnel_add_t udp_tunnel_add;
1420  eth_udp_tunnel_del_t udp_tunnel_del;
1421  eth_set_queue_rate_limit_t set_queue_rate_limit;
1422  eth_set_vf_rate_limit_t set_vf_rate_limit;
1425  fdir_add_signature_filter_t fdir_add_signature_filter;
1427  fdir_update_signature_filter_t fdir_update_signature_filter;
1429  fdir_remove_signature_filter_t fdir_remove_signature_filter;
1431  fdir_infos_get_t fdir_infos_get;
1433  fdir_add_perfect_filter_t fdir_add_perfect_filter;
1435  fdir_update_perfect_filter_t fdir_update_perfect_filter;
1437  fdir_remove_perfect_filter_t fdir_remove_perfect_filter;
1439  fdir_set_masks_t fdir_set_masks;
1441  reta_update_t reta_update;
1443  reta_query_t reta_query;
1444 
1445  eth_get_reg_length_t get_reg_length;
1447  eth_get_reg_t get_reg;
1449  eth_get_eeprom_length_t get_eeprom_length;
1451  eth_get_eeprom_t get_eeprom;
1453  eth_set_eeprom_t set_eeprom;
1455  /* bypass control */
1456 #ifdef RTE_NIC_BYPASS
1457  bypass_init_t bypass_init;
1458  bypass_state_set_t bypass_state_set;
1459  bypass_state_show_t bypass_state_show;
1460  bypass_event_set_t bypass_event_set;
1461  bypass_event_show_t bypass_event_show;
1462  bypass_wd_timeout_set_t bypass_wd_timeout_set;
1463  bypass_wd_timeout_show_t bypass_wd_timeout_show;
1464  bypass_ver_show_t bypass_ver_show;
1465  bypass_wd_reset_t bypass_wd_reset;
1466 #endif
1467 
1469  rss_hash_update_t rss_hash_update;
1471  rss_hash_conf_get_t rss_hash_conf_get;
1472  eth_filter_ctrl_t filter_ctrl;
1473  eth_set_mc_addr_list_t set_mc_addr_list;
1476  eth_timesync_enable_t timesync_enable;
1478  eth_timesync_disable_t timesync_disable;
1480  eth_timesync_read_rx_timestamp_t timesync_read_rx_timestamp;
1482  eth_timesync_read_tx_timestamp_t timesync_read_tx_timestamp;
1483 };
1484 
1507 typedef uint16_t (*rte_rx_callback_fn)(uint8_t port, uint16_t queue,
1508  struct rte_mbuf *pkts[], uint16_t nb_pkts, uint16_t max_pkts,
1509  void *user_param);
1510 
1531 typedef uint16_t (*rte_tx_callback_fn)(uint8_t port, uint16_t queue,
1532  struct rte_mbuf *pkts[], uint16_t nb_pkts, void *user_param);
1533 
1539 struct rte_eth_rxtx_callback {
1540  struct rte_eth_rxtx_callback *next;
1541  union{
1542  rte_rx_callback_fn rx;
1543  rte_tx_callback_fn tx;
1544  } fn;
1545  void *param;
1546 };
1547 
1551 enum rte_eth_dev_type {
1552  RTE_ETH_DEV_UNKNOWN,
1553  RTE_ETH_DEV_PCI,
1555  RTE_ETH_DEV_VIRTUAL,
1556  RTE_ETH_DEV_MAX
1557 };
1558 
1569 struct rte_eth_dev {
1570  eth_rx_burst_t rx_pkt_burst;
1571  eth_tx_burst_t tx_pkt_burst;
1572  struct rte_eth_dev_data *data;
1573  const struct eth_driver *driver;
1574  const struct eth_dev_ops *dev_ops;
1575  struct rte_pci_device *pci_dev;
1577  struct rte_eth_dev_cb_list link_intr_cbs;
1582  struct rte_eth_rxtx_callback *post_rx_burst_cbs[RTE_MAX_QUEUES_PER_PORT];
1587  struct rte_eth_rxtx_callback *pre_tx_burst_cbs[RTE_MAX_QUEUES_PER_PORT];
1588  uint8_t attached;
1589  enum rte_eth_dev_type dev_type;
1590 };
1591 
1592 struct rte_eth_dev_sriov {
1593  uint8_t active;
1594  uint8_t nb_q_per_pool;
1595  uint16_t def_vmdq_idx;
1596  uint16_t def_pool_q_idx;
1597 };
1598 #define RTE_ETH_DEV_SRIOV(dev) ((dev)->data->sriov)
1599 
1600 #define RTE_ETH_NAME_MAX_LEN (32)
1601 
1609 struct rte_eth_dev_data {
1610  char name[RTE_ETH_NAME_MAX_LEN];
1612  void **rx_queues;
1613  void **tx_queues;
1614  uint16_t nb_rx_queues;
1615  uint16_t nb_tx_queues;
1617  struct rte_eth_dev_sriov sriov;
1619  void *dev_private;
1621  struct rte_eth_link dev_link;
1624  struct rte_eth_conf dev_conf;
1625  uint16_t mtu;
1627  uint32_t min_rx_buf_size;
1630  uint64_t rx_mbuf_alloc_failed;
1631  struct ether_addr* mac_addrs;
1632  uint64_t mac_pool_sel[ETH_NUM_RECEIVE_MAC_ADDR];
1634  struct ether_addr* hash_mac_addrs;
1636  uint8_t port_id;
1637  uint8_t promiscuous : 1,
1638  scattered_rx : 1,
1639  all_multicast : 1,
1640  dev_started : 1,
1641  lro : 1;
1642 };
1643 
1649 extern struct rte_eth_dev rte_eth_devices[];
1650 
1664 extern uint8_t rte_eth_dev_count(void);
1665 
1675 extern struct rte_eth_dev *rte_eth_dev_allocated(const char *name);
1676 
1687 struct rte_eth_dev *rte_eth_dev_allocate(const char *name,
1688  enum rte_eth_dev_type type);
1689 
1699 int rte_eth_dev_release_port(struct rte_eth_dev *eth_dev);
1700 
1713 int rte_eth_dev_attach(const char *devargs, uint8_t *port_id);
1714 
1727 int rte_eth_dev_detach(uint8_t port_id, char *devname);
1728 
1729 struct eth_driver;
1760 typedef int (*eth_dev_init_t)(struct rte_eth_dev *eth_dev);
1761 
1777 typedef int (*eth_dev_uninit_t)(struct rte_eth_dev *eth_dev);
1778 
1794 struct eth_driver {
1795  struct rte_pci_driver pci_drv;
1796  eth_dev_init_t eth_dev_init;
1797  eth_dev_uninit_t eth_dev_uninit;
1798  unsigned int dev_private_size;
1799 };
1800 
1811 extern void rte_eth_driver_register(struct eth_driver *eth_drv);
1812 
1842 extern int rte_eth_dev_configure(uint8_t port_id,
1843  uint16_t nb_rx_queue,
1844  uint16_t nb_tx_queue,
1845  const struct rte_eth_conf *eth_conf);
1846 
1886 extern int rte_eth_rx_queue_setup(uint8_t port_id, uint16_t rx_queue_id,
1887  uint16_t nb_rx_desc, unsigned int socket_id,
1888  const struct rte_eth_rxconf *rx_conf,
1889  struct rte_mempool *mb_pool);
1890 
1934 extern int rte_eth_tx_queue_setup(uint8_t port_id, uint16_t tx_queue_id,
1935  uint16_t nb_tx_desc, unsigned int socket_id,
1936  const struct rte_eth_txconf *tx_conf);
1937 
1938 /*
1939  * Return the NUMA socket to which an Ethernet device is connected
1940  *
1941  * @param port_id
1942  * The port identifier of the Ethernet device
1943  * @return
1944  * The NUMA socket id to which the Ethernet device is connected or
1945  * a default of zero if the socket could not be determined.
1946  * -1 is returned is the port_id value is out of range.
1947  */
1948 extern int rte_eth_dev_socket_id(uint8_t port_id);
1949 
1950 /*
1951  * Check if port_id of device is attached
1952  *
1953  * @param port_id
1954  * The port identifier of the Ethernet device
1955  * @return
1956  * - 0 if port is out of range or not attached
1957  * - 1 if device is attached
1958  */
1959 extern int rte_eth_dev_is_valid_port(uint8_t port_id);
1960 
1961 /*
1962  * Allocate mbuf from mempool, setup the DMA physical address
1963  * and then start RX for specified queue of a port. It is used
1964  * when rx_deferred_start flag of the specified queue is true.
1965  *
1966  * @param port_id
1967  * The port identifier of the Ethernet device
1968  * @param rx_queue_id
1969  * The index of the rx queue to update the ring.
1970  * The value must be in the range [0, nb_rx_queue - 1] previously supplied
1971  * to rte_eth_dev_configure().
1972  * @return
1973  * - 0: Success, the transmit queue is correctly set up.
1974  * - -EINVAL: The port_id or the queue_id out of range.
1975  * - -ENOTSUP: The function not supported in PMD driver.
1976  */
1977 extern int rte_eth_dev_rx_queue_start(uint8_t port_id, uint16_t rx_queue_id);
1978 
1979 /*
1980  * Stop specified RX queue of a port
1981  *
1982  * @param port_id
1983  * The port identifier of the Ethernet device
1984  * @param rx_queue_id
1985  * The index of the rx queue to update the ring.
1986  * The value must be in the range [0, nb_rx_queue - 1] previously supplied
1987  * to rte_eth_dev_configure().
1988  * @return
1989  * - 0: Success, the transmit queue is correctly set up.
1990  * - -EINVAL: The port_id or the queue_id out of range.
1991  * - -ENOTSUP: The function not supported in PMD driver.
1992  */
1993 extern int rte_eth_dev_rx_queue_stop(uint8_t port_id, uint16_t rx_queue_id);
1994 
1995 /*
1996  * Start TX for specified queue of a port. It is used when tx_deferred_start
1997  * flag of the specified queue is true.
1998  *
1999  * @param port_id
2000  * The port identifier of the Ethernet device
2001  * @param tx_queue_id
2002  * The index of the tx queue to update the ring.
2003  * The value must be in the range [0, nb_tx_queue - 1] previously supplied
2004  * to rte_eth_dev_configure().
2005  * @return
2006  * - 0: Success, the transmit queue is correctly set up.
2007  * - -EINVAL: The port_id or the queue_id out of range.
2008  * - -ENOTSUP: The function not supported in PMD driver.
2009  */
2010 extern int rte_eth_dev_tx_queue_start(uint8_t port_id, uint16_t tx_queue_id);
2011 
2012 /*
2013  * Stop specified TX queue of a port
2014  *
2015  * @param port_id
2016  * The port identifier of the Ethernet device
2017  * @param tx_queue_id
2018  * The index of the tx queue to update the ring.
2019  * The value must be in the range [0, nb_tx_queue - 1] previously supplied
2020  * to rte_eth_dev_configure().
2021  * @return
2022  * - 0: Success, the transmit queue is correctly set up.
2023  * - -EINVAL: The port_id or the queue_id out of range.
2024  * - -ENOTSUP: The function not supported in PMD driver.
2025  */
2026 extern int rte_eth_dev_tx_queue_stop(uint8_t port_id, uint16_t tx_queue_id);
2027 
2028 
2029 
2045 extern int rte_eth_dev_start(uint8_t port_id);
2046 
2054 extern void rte_eth_dev_stop(uint8_t port_id);
2055 
2056 
2069 extern int rte_eth_dev_set_link_up(uint8_t port_id);
2070 
2080 extern int rte_eth_dev_set_link_down(uint8_t port_id);
2081 
2090 extern void rte_eth_dev_close(uint8_t port_id);
2091 
2098 extern void rte_eth_promiscuous_enable(uint8_t port_id);
2099 
2106 extern void rte_eth_promiscuous_disable(uint8_t port_id);
2107 
2118 extern int rte_eth_promiscuous_get(uint8_t port_id);
2119 
2126 extern void rte_eth_allmulticast_enable(uint8_t port_id);
2127 
2134 extern void rte_eth_allmulticast_disable(uint8_t port_id);
2135 
2146 extern int rte_eth_allmulticast_get(uint8_t port_id);
2147 
2159 extern void rte_eth_link_get(uint8_t port_id, struct rte_eth_link *link);
2160 
2172 extern void rte_eth_link_get_nowait(uint8_t port_id,
2173  struct rte_eth_link *link);
2174 
2192 extern int rte_eth_stats_get(uint8_t port_id, struct rte_eth_stats *stats);
2193 
2200 extern void rte_eth_stats_reset(uint8_t port_id);
2201 
2223 extern int rte_eth_xstats_get(uint8_t port_id,
2224  struct rte_eth_xstats *xstats, unsigned n);
2225 
2232 extern void rte_eth_xstats_reset(uint8_t port_id);
2233 
2251 extern int rte_eth_dev_set_tx_queue_stats_mapping(uint8_t port_id,
2252  uint16_t tx_queue_id,
2253  uint8_t stat_idx);
2254 
2272 extern int rte_eth_dev_set_rx_queue_stats_mapping(uint8_t port_id,
2273  uint16_t rx_queue_id,
2274  uint8_t stat_idx);
2275 
2285 extern void rte_eth_macaddr_get(uint8_t port_id, struct ether_addr *mac_addr);
2286 
2296 extern void rte_eth_dev_info_get(uint8_t port_id,
2297  struct rte_eth_dev_info *dev_info);
2298 
2310 extern int rte_eth_dev_get_mtu(uint8_t port_id, uint16_t *mtu);
2311 
2325 extern int rte_eth_dev_set_mtu(uint8_t port_id, uint16_t mtu);
2326 
2345 extern int rte_eth_dev_vlan_filter(uint8_t port_id, uint16_t vlan_id , int on);
2346 
2366 extern int rte_eth_dev_set_vlan_strip_on_queue(uint8_t port_id,
2367  uint16_t rx_queue_id, int on);
2368 
2383 extern int rte_eth_dev_set_vlan_ether_type(uint8_t port_id, uint16_t tag_type);
2384 
2405 extern int rte_eth_dev_set_vlan_offload(uint8_t port_id, int offload_mask);
2406 
2419 extern int rte_eth_dev_get_vlan_offload(uint8_t port_id);
2420 
2435 extern int rte_eth_dev_set_vlan_pvid(uint8_t port_id, uint16_t pvid, int on);
2436 
2519 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2520 extern uint16_t rte_eth_rx_burst(uint8_t port_id, uint16_t queue_id,
2521  struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
2522 #else
2523 static inline uint16_t
2524 rte_eth_rx_burst(uint8_t port_id, uint16_t queue_id,
2525  struct rte_mbuf **rx_pkts, const uint16_t nb_pkts)
2526 {
2527  struct rte_eth_dev *dev;
2528 
2529  dev = &rte_eth_devices[port_id];
2530 
2531  int16_t nb_rx = (*dev->rx_pkt_burst)(dev->data->rx_queues[queue_id],
2532  rx_pkts, nb_pkts);
2533 
2534 #ifdef RTE_ETHDEV_RXTX_CALLBACKS
2535  struct rte_eth_rxtx_callback *cb = dev->post_rx_burst_cbs[queue_id];
2536 
2537  if (unlikely(cb != NULL)) {
2538  do {
2539  nb_rx = cb->fn.rx(port_id, queue_id, rx_pkts, nb_rx,
2540  nb_pkts, cb->param);
2541  cb = cb->next;
2542  } while (cb != NULL);
2543  }
2544 #endif
2545 
2546  return nb_rx;
2547 }
2548 #endif
2549 
2560 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2561 extern uint32_t rte_eth_rx_queue_count(uint8_t port_id, uint16_t queue_id);
2562 #else
2563 static inline uint32_t
2564 rte_eth_rx_queue_count(uint8_t port_id, uint16_t queue_id)
2565 {
2566  struct rte_eth_dev *dev;
2567 
2568  dev = &rte_eth_devices[port_id];
2569  return (*dev->dev_ops->rx_queue_count)(dev, queue_id);
2570 }
2571 #endif
2572 
2587 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2588 extern int rte_eth_rx_descriptor_done(uint8_t port_id,
2589  uint16_t queue_id,
2590  uint16_t offset);
2591 #else
2592 static inline int
2593 rte_eth_rx_descriptor_done(uint8_t port_id, uint16_t queue_id, uint16_t offset)
2594 {
2595  struct rte_eth_dev *dev;
2596 
2597  dev = &rte_eth_devices[port_id];
2598  return (*dev->dev_ops->rx_descriptor_done)( \
2599  dev->data->rx_queues[queue_id], offset);
2600 }
2601 #endif
2602 
2661 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2662 extern uint16_t rte_eth_tx_burst(uint8_t port_id, uint16_t queue_id,
2663  struct rte_mbuf **tx_pkts, uint16_t nb_pkts);
2664 #else
2665 static inline uint16_t
2666 rte_eth_tx_burst(uint8_t port_id, uint16_t queue_id,
2667  struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
2668 {
2669  struct rte_eth_dev *dev;
2670 
2671  dev = &rte_eth_devices[port_id];
2672 
2673 #ifdef RTE_ETHDEV_RXTX_CALLBACKS
2674  struct rte_eth_rxtx_callback *cb = dev->pre_tx_burst_cbs[queue_id];
2675 
2676  if (unlikely(cb != NULL)) {
2677  do {
2678  nb_pkts = cb->fn.tx(port_id, queue_id, tx_pkts, nb_pkts,
2679  cb->param);
2680  cb = cb->next;
2681  } while (cb != NULL);
2682  }
2683 #endif
2684 
2685  return (*dev->tx_pkt_burst)(dev->data->tx_queues[queue_id], tx_pkts, nb_pkts);
2686 }
2687 #endif
2688 
2711 int rte_eth_dev_fdir_add_signature_filter(uint8_t port_id,
2712  struct rte_fdir_filter *fdir_filter,
2713  uint8_t rx_queue);
2714 
2737 int rte_eth_dev_fdir_update_signature_filter(uint8_t port_id,
2738  struct rte_fdir_filter *fdir_ftr,
2739  uint8_t rx_queue);
2740 
2759 int rte_eth_dev_fdir_remove_signature_filter(uint8_t port_id,
2760  struct rte_fdir_filter *fdir_ftr);
2761 
2776 int rte_eth_dev_fdir_get_infos(uint8_t port_id, struct rte_eth_fdir *fdir);
2777 
2806 int rte_eth_dev_fdir_add_perfect_filter(uint8_t port_id,
2807  struct rte_fdir_filter *fdir_filter,
2808  uint16_t soft_id, uint8_t rx_queue,
2809  uint8_t drop);
2810 
2840 int rte_eth_dev_fdir_update_perfect_filter(uint8_t port_id,
2841  struct rte_fdir_filter *fdir_filter,
2842  uint16_t soft_id, uint8_t rx_queue,
2843  uint8_t drop);
2844 
2866 int rte_eth_dev_fdir_remove_perfect_filter(uint8_t port_id,
2867  struct rte_fdir_filter *fdir_filter,
2868  uint16_t soft_id);
2902 int rte_eth_dev_fdir_set_masks(uint8_t port_id,
2903  struct rte_fdir_masks *fdir_mask);
2904 
2908 enum rte_eth_event_type {
2909  RTE_ETH_EVENT_UNKNOWN,
2910  RTE_ETH_EVENT_INTR_LSC,
2911  RTE_ETH_EVENT_MAX
2912 };
2913 
2914 typedef void (*rte_eth_dev_cb_fn)(uint8_t port_id, \
2915  enum rte_eth_event_type event, void *cb_arg);
2936 int rte_eth_dev_callback_register(uint8_t port_id,
2937  enum rte_eth_event_type event,
2938  rte_eth_dev_cb_fn cb_fn, void *cb_arg);
2939 
2957 int rte_eth_dev_callback_unregister(uint8_t port_id,
2958  enum rte_eth_event_type event,
2959  rte_eth_dev_cb_fn cb_fn, void *cb_arg);
2960 
2974 void _rte_eth_dev_callback_process(struct rte_eth_dev *dev,
2975  enum rte_eth_event_type event);
2976 
2997 int rte_eth_dev_rx_intr_enable(uint8_t port_id, uint16_t queue_id);
2998 
3018 int rte_eth_dev_rx_intr_disable(uint8_t port_id, uint16_t queue_id);
3019 
3037 int rte_eth_dev_rx_intr_ctl(uint8_t port_id, int epfd, int op, void *data);
3038 
3060 int rte_eth_dev_rx_intr_ctl_q(uint8_t port_id, uint16_t queue_id,
3061  int epfd, int op, void *data);
3062 
3075 int rte_eth_led_on(uint8_t port_id);
3076 
3089 int rte_eth_led_off(uint8_t port_id);
3090 
3103 int rte_eth_dev_flow_ctrl_get(uint8_t port_id,
3104  struct rte_eth_fc_conf *fc_conf);
3105 
3120 int rte_eth_dev_flow_ctrl_set(uint8_t port_id,
3121  struct rte_eth_fc_conf *fc_conf);
3122 
3138 int rte_eth_dev_priority_flow_ctrl_set(uint8_t port_id,
3139  struct rte_eth_pfc_conf *pfc_conf);
3140 
3159 int rte_eth_dev_mac_addr_add(uint8_t port, struct ether_addr *mac_addr,
3160  uint32_t pool);
3161 
3175 int rte_eth_dev_mac_addr_remove(uint8_t port, struct ether_addr *mac_addr);
3176 
3190 int rte_eth_dev_default_mac_addr_set(uint8_t port, struct ether_addr *mac_addr);
3191 
3192 
3208 int rte_eth_dev_rss_reta_update(uint8_t port,
3209  struct rte_eth_rss_reta_entry64 *reta_conf,
3210  uint16_t reta_size);
3211 
3227 int rte_eth_dev_rss_reta_query(uint8_t port,
3228  struct rte_eth_rss_reta_entry64 *reta_conf,
3229  uint16_t reta_size);
3230 
3249 int rte_eth_dev_uc_hash_table_set(uint8_t port,struct ether_addr *addr,
3250  uint8_t on);
3251 
3269 int rte_eth_dev_uc_all_hash_table_set(uint8_t port,uint8_t on);
3270 
3293 int rte_eth_dev_set_vf_rxmode(uint8_t port, uint16_t vf, uint16_t rx_mode,
3294  uint8_t on);
3295 
3312 int
3313 rte_eth_dev_set_vf_tx(uint8_t port,uint16_t vf, uint8_t on);
3314 
3331 int
3332 rte_eth_dev_set_vf_rx(uint8_t port,uint16_t vf, uint8_t on);
3333 
3353 int
3354 rte_eth_dev_set_vf_vlan_filter(uint8_t port, uint16_t vlan_id,
3355  uint64_t vf_mask,
3356  uint8_t vlan_on);
3357 
3379 int rte_eth_mirror_rule_set(uint8_t port_id,
3380  struct rte_eth_mirror_conf *mirror_conf,
3381  uint8_t rule_id,
3382  uint8_t on);
3383 
3397 int rte_eth_mirror_rule_reset(uint8_t port_id,
3398  uint8_t rule_id);
3399 
3415 int rte_eth_set_queue_rate_limit(uint8_t port_id, uint16_t queue_idx,
3416  uint16_t tx_rate);
3417 
3435 int rte_eth_set_vf_rate_limit(uint8_t port_id, uint16_t vf,
3436  uint16_t tx_rate, uint64_t q_msk);
3437 
3449 int rte_eth_dev_bypass_init(uint8_t port);
3450 
3466 int rte_eth_dev_bypass_state_show(uint8_t port, uint32_t *state);
3467 
3483 int rte_eth_dev_bypass_state_set(uint8_t port, uint32_t *new_state);
3484 
3507 int rte_eth_dev_bypass_event_show(uint8_t port, uint32_t event, uint32_t *state);
3508 
3531 int rte_eth_dev_bypass_event_store(uint8_t port, uint32_t event, uint32_t state);
3532 
3553 int rte_eth_dev_wd_timeout_store(uint8_t port, uint32_t timeout);
3554 
3567 int rte_eth_dev_bypass_ver_show(uint8_t port, uint32_t *ver);
3568 
3589 int rte_eth_dev_bypass_wd_timeout_show(uint8_t port, uint32_t *wd_timeout);
3590 
3601 int rte_eth_dev_bypass_wd_reset(uint8_t port);
3602 
3616 int rte_eth_dev_rss_hash_update(uint8_t port_id,
3617  struct rte_eth_rss_conf *rss_conf);
3618 
3632 int
3633 rte_eth_dev_rss_hash_conf_get(uint8_t port_id,
3634  struct rte_eth_rss_conf *rss_conf);
3635 
3650 int
3651 rte_eth_dev_udp_tunnel_add(uint8_t port_id,
3652  struct rte_eth_udp_tunnel *tunnel_udp);
3653 
3667 int
3668 rte_eth_dev_udp_tunnel_delete(uint8_t port_id,
3669  struct rte_eth_udp_tunnel *tunnel_udp);
3670 
3684 int rte_eth_dev_filter_supported(uint8_t port_id, enum rte_filter_type filter_type);
3685 
3704 int rte_eth_dev_filter_ctrl(uint8_t port_id, enum rte_filter_type filter_type,
3705  enum rte_filter_op filter_op, void *arg);
3706 
3731 void *rte_eth_add_rx_callback(uint8_t port_id, uint16_t queue_id,
3732  rte_rx_callback_fn fn, void *user_param);
3733 
3758 void *rte_eth_add_tx_callback(uint8_t port_id, uint16_t queue_id,
3759  rte_tx_callback_fn fn, void *user_param);
3760 
3791 int rte_eth_remove_rx_callback(uint8_t port_id, uint16_t queue_id,
3792  struct rte_eth_rxtx_callback *user_cb);
3793 
3824 int rte_eth_remove_tx_callback(uint8_t port_id, uint16_t queue_id,
3825  struct rte_eth_rxtx_callback *user_cb);
3826 
3838 int rte_eth_dev_get_reg_length(uint8_t port_id);
3839 
3853 int rte_eth_dev_get_reg_info(uint8_t port_id, struct rte_dev_reg_info *info);
3854 
3866 int rte_eth_dev_get_eeprom_length(uint8_t port_id);
3867 
3882 int rte_eth_dev_get_eeprom(uint8_t port_id, struct rte_dev_eeprom_info *info);
3883 
3898 int rte_eth_dev_set_eeprom(uint8_t port_id, struct rte_dev_eeprom_info *info);
3899 
3917 int rte_eth_dev_set_mc_addr_list(uint8_t port_id,
3918  struct ether_addr *mc_addr_set,
3919  uint32_t nb_mc_addr);
3920 
3932 extern int rte_eth_timesync_enable(uint8_t port_id);
3933 
3945 extern int rte_eth_timesync_disable(uint8_t port_id);
3946 
3964 extern int rte_eth_timesync_read_rx_timestamp(uint8_t port_id,
3965  struct timespec *timestamp,
3966  uint32_t flags);
3967 
3982 extern int rte_eth_timesync_read_tx_timestamp(uint8_t port_id,
3983  struct timespec *timestamp);
3984 
3985 #ifdef __cplusplus
3986 }
3987 #endif
3988 
3989 #endif /* _RTE_ETHDEV_H_ */
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