DPDK  24.11.0-rc1
rte_higig.h
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1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(C) 2019 Marvell International Ltd.
3  */
4 
5 #ifndef _RTE_HIGIG_H_
6 #define _RTE_HIGIG_H_
7 
16 #include <stdint.h>
17 #include <rte_byteorder.h>
18 
24 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
25  uint32_t ksop:8;
26  uint32_t tc:4;
27  uint32_t mcst:1;
28  uint32_t resv:3;
29  uint32_t dst_modid:8;
30  uint32_t dst_pid:8;
31  uint32_t src_modid:8;
32  uint32_t src_pid:8;
33  uint32_t lbid:8;
34  uint32_t ppd_type:3;
35  uint32_t resv1:3;
36  uint32_t dp:2;
37 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
38  uint32_t ksop:8;
39  uint32_t resv:3;
40  uint32_t mcst:1;
41  uint32_t tc:4;
42  uint32_t dst_modid:8;
43  uint32_t dst_pid:8;
44  uint32_t src_modid:8;
45  uint32_t src_pid:8;
46  uint32_t lbid:8;
47  uint32_t dp:2;
48  uint32_t resv1:3;
49  uint32_t ppd_type:3;
50 #endif
51 };
52 
53 
59 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
60  uint32_t mirror:1;
61  uint32_t mirror_done:1;
62  uint32_t mirror_only:1;
63  uint32_t ingress_tagged:1;
64  uint32_t dst_tgid:3;
65  uint32_t dst_t:1;
66  uint32_t vc_label2:4;
67  uint32_t label_present:1;
68  uint32_t l3:1;
69  uint32_t res:2;
70  uint32_t vc_label1:8;
71  uint32_t vc_label0:8;
72  uint32_t vid_high:8;
73  uint32_t vid_low:8;
74  uint32_t opc:3;
75  uint32_t res1:2;
76  uint32_t srce_t:1;
77  uint32_t pf:2;
78  uint32_t res2:5;
79  uint32_t hdr_ext_length:3;
80 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
81  uint32_t dst_t:1;
82  uint32_t dst_tgid:3;
83  uint32_t ingress_tagged:1;
84  uint32_t mirror_only:1;
85  uint32_t mirror_done:1;
86  uint32_t mirror:1;
87  uint32_t res:2;
88  uint32_t l3:1;
89  uint32_t label_present:1;
90  uint32_t vc_label2:4;
91  uint32_t vc_label1:8;
92  uint32_t vc_label0:8;
93  uint32_t vid_high:8;
94  uint32_t vid_low:8;
95  uint32_t pf:2;
96  uint32_t srce_t:1;
97  uint32_t res1:2;
98  uint32_t opc:3;
99  uint32_t hdr_ext_length:3;
100  uint32_t res2:5;
101 #endif
102 };
103 
104 
109 __extension__
111  rte_be16_t classification;
112  rte_be16_t resv;
113  rte_be16_t vid;
114 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
115  uint16_t opcode:3;
116  uint16_t resv1:2;
117  uint16_t src_t:1;
118  uint16_t pfm:2;
119  uint16_t resv2:5;
120  uint16_t hdr_ext_len:3;
121 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN
122  uint16_t pfm:2;
123  uint16_t src_t:1;
124  uint16_t resv1:2;
125  uint16_t opcode:3;
126  uint16_t hdr_ext_len:3;
127  uint16_t resv2:5;
128 #endif
129 };
130 
136  struct rte_higig2_frc fcr;
137  union {
138  struct rte_higig2_ppt_type0 ppt0;
139  struct rte_higig2_ppt_type1 ppt1;
140  };
141 };
142 
143 #endif /* RTE_HIGIG_H_ */
uint16_t rte_be16_t