|
DPDK
24.07.0
|
Go to the source code of this file.
Functions | |
| static uint8_t | rte_read8_relaxed (const volatile void *addr) |
| static uint16_t | rte_read16_relaxed (const volatile void *addr) |
| static uint32_t | rte_read32_relaxed (const volatile void *addr) |
| static uint64_t | rte_read64_relaxed (const volatile void *addr) |
| static void | rte_write8_relaxed (uint8_t value, volatile void *addr) |
| static void | rte_write16_relaxed (uint16_t value, volatile void *addr) |
| static void | rte_write32_relaxed (uint32_t value, volatile void *addr) |
| static void | rte_write64_relaxed (uint64_t value, volatile void *addr) |
| static uint8_t | rte_read8 (const volatile void *addr) |
| static uint16_t | rte_read16 (const volatile void *addr) |
| static uint32_t | rte_read32 (const volatile void *addr) |
| static uint64_t | rte_read64 (const volatile void *addr) |
| static void | rte_write8 (uint8_t value, volatile void *addr) |
| static void | rte_write16 (uint16_t value, volatile void *addr) |
| static void | rte_write32 (uint32_t value, volatile void *addr) |
| static void | rte_write64 (uint64_t value, volatile void *addr) |
| static __rte_experimental void | rte_write32_wc (uint32_t value, volatile void *addr) |
| static __rte_experimental void | rte_write32_wc_relaxed (uint32_t value, volatile void *addr) |
I/O device memory operations
This file defines the generic API for I/O device memory read/write operations
Definition in file rte_io.h.
|
inlinestatic |
Read a 8-bit value from I/O device memory address addr.
The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access.
| addr | I/O memory address to read the value from |
|
inlinestatic |
Read a 16-bit value from I/O device memory address addr.
The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access.
| addr | I/O memory address to read the value from |
|
inlinestatic |
Read a 32-bit value from I/O device memory address addr.
The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access.
| addr | I/O memory address to read the value from |
|
inlinestatic |
Read a 64-bit value from I/O device memory address addr.
The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access.
| addr | I/O memory address to read the value from |
|
inlinestatic |
Write a 8-bit value to I/O device memory address addr.
The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access.
| value | Value to write |
| addr | I/O memory address to write the value to |
|
inlinestatic |
Write a 16-bit value to I/O device memory address addr.
The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access.
| value | Value to write |
| addr | I/O memory address to write the value to |
|
inlinestatic |
Write a 32-bit value to I/O device memory address addr.
The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access.
| value | Value to write |
| addr | I/O memory address to write the value to |
|
inlinestatic |
Write a 64-bit value to I/O device memory address addr.
The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access.
| value | Value to write |
| addr | I/O memory address to write the value to |
|
inlinestatic |
|
inlinestatic |
|
inlinestatic |
|
inlinestatic |
|
inlinestatic |
|
inlinestatic |
|
inlinestatic |
|
inlinestatic |
|
inlinestatic |
Write a 32-bit value to I/O device memory address addr using write combining memory write protocol. Depending on the platform write combining may not be available and/or may be treated as a hint and the behavior may fallback to a regular store.
| value | Value to write |
| addr | I/O memory address to write the value to |
|
inlinestatic |
Write a 32-bit value to I/O device memory address addr using write combining memory write protocol. Depending on the platform write combining may not be available and/or may be treated as a hint and the behavior may fallback to a regular store.
The relaxed version does not have additional I/O memory barrier, useful in accessing the device registers of integrated controllers which implicitly strongly ordered with respect to memory access.
| value | Value to write |
| addr | I/O memory address to write the value to |
1.8.13