rte_atomic.h

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/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2010-2014 Intel Corporation
 */

#ifndef _RTE_ATOMIC_H_
#define _RTE_ATOMIC_H_

#include <stdint.h>

#include <rte_common.h>
#include <rte_stdatomic.h>

#ifdef __DOXYGEN__


static inline void rte_mb(void);

static inline void rte_wmb(void);

static inline void rte_rmb(void);


static inline void rte_smp_mb(void);

static inline void rte_smp_wmb(void);

static inline void rte_smp_rmb(void);


static inline void rte_io_mb(void);

static inline void rte_io_wmb(void);

static inline void rte_io_rmb(void);

#endif /* __DOXYGEN__ */

#ifdef RTE_TOOLCHAIN_MSVC
#define rte_compiler_barrier() _ReadWriteBarrier()
#else
#define rte_compiler_barrier() do {     \
    asm volatile ("" : : : "memory");   \
} while(0)
#endif

static inline void rte_atomic_thread_fence(rte_memory_order memorder);

/*------------------------- 16 bit atomic operations -------------------------*/

#ifndef RTE_TOOLCHAIN_MSVC

static inline int
rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src);

#ifdef RTE_FORCE_INTRINSICS
static inline int
rte_atomic16_cmpset(volatile uint16_t *dst, uint16_t exp, uint16_t src)
{
    return __sync_bool_compare_and_swap(dst, exp, src);
}
#endif

static inline uint16_t
rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val);

#ifdef RTE_FORCE_INTRINSICS
static inline uint16_t
rte_atomic16_exchange(volatile uint16_t *dst, uint16_t val)
{
    return rte_atomic_exchange_explicit(dst, val, rte_memory_order_seq_cst);
}
#endif

typedef struct {
    volatile int16_t cnt; 
} rte_atomic16_t;

#define RTE_ATOMIC16_INIT(val) { (val) }

static inline void
rte_atomic16_init(rte_atomic16_t *v)
{
    v->cnt = 0;
}

static inline int16_t
rte_atomic16_read(const rte_atomic16_t *v)
{
    return v->cnt;
}

static inline void
rte_atomic16_set(rte_atomic16_t *v, int16_t new_value)
{
    v->cnt = new_value;
}

static inline void
rte_atomic16_add(rte_atomic16_t *v, int16_t inc)
{
    rte_atomic_fetch_add_explicit((volatile __rte_atomic int16_t *)&v->cnt, inc,
        rte_memory_order_seq_cst);
}

static inline void
rte_atomic16_sub(rte_atomic16_t *v, int16_t dec)
{
    rte_atomic_fetch_sub_explicit((volatile __rte_atomic int16_t *)&v->cnt, dec,
        rte_memory_order_seq_cst);
}

static inline void
rte_atomic16_inc(rte_atomic16_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline void
rte_atomic16_inc(rte_atomic16_t *v)
{
    rte_atomic16_add(v, 1);
}
#endif

static inline void
rte_atomic16_dec(rte_atomic16_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline void
rte_atomic16_dec(rte_atomic16_t *v)
{
    rte_atomic16_sub(v, 1);
}
#endif

static inline int16_t
rte_atomic16_add_return(rte_atomic16_t *v, int16_t inc)
{
    return rte_atomic_fetch_add_explicit((volatile __rte_atomic int16_t *)&v->cnt, inc,
        rte_memory_order_seq_cst) + inc;
}

static inline int16_t
rte_atomic16_sub_return(rte_atomic16_t *v, int16_t dec)
{
    return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int16_t *)&v->cnt, dec,
        rte_memory_order_seq_cst) - dec;
}

static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline int rte_atomic16_inc_and_test(rte_atomic16_t *v)
{
    return rte_atomic_fetch_add_explicit((volatile __rte_atomic int16_t *)&v->cnt, 1,
        rte_memory_order_seq_cst) + 1 == 0;
}
#endif

static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline int rte_atomic16_dec_and_test(rte_atomic16_t *v)
{
    return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int16_t *)&v->cnt, 1,
        rte_memory_order_seq_cst) - 1 == 0;
}
#endif

static inline int rte_atomic16_test_and_set(rte_atomic16_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline int rte_atomic16_test_and_set(rte_atomic16_t *v)
{
    return rte_atomic16_cmpset((volatile uint16_t *)&v->cnt, 0, 1);
}
#endif

static inline void rte_atomic16_clear(rte_atomic16_t *v)
{
    v->cnt = 0;
}

/*------------------------- 32 bit atomic operations -------------------------*/

static inline int
rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src);

#ifdef RTE_FORCE_INTRINSICS
static inline int
rte_atomic32_cmpset(volatile uint32_t *dst, uint32_t exp, uint32_t src)
{
    return __sync_bool_compare_and_swap(dst, exp, src);
}
#endif

static inline uint32_t
rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val);

#ifdef RTE_FORCE_INTRINSICS
static inline uint32_t
rte_atomic32_exchange(volatile uint32_t *dst, uint32_t val)
{
    return rte_atomic_exchange_explicit(dst, val, rte_memory_order_seq_cst);
}
#endif

typedef struct {
    volatile int32_t cnt; 
} rte_atomic32_t;

#define RTE_ATOMIC32_INIT(val) { (val) }

static inline void
rte_atomic32_init(rte_atomic32_t *v)
{
    v->cnt = 0;
}

static inline int32_t
rte_atomic32_read(const rte_atomic32_t *v)
{
    return v->cnt;
}

static inline void
rte_atomic32_set(rte_atomic32_t *v, int32_t new_value)
{
    v->cnt = new_value;
}

static inline void
rte_atomic32_add(rte_atomic32_t *v, int32_t inc)
{
    rte_atomic_fetch_add_explicit((volatile __rte_atomic int32_t *)&v->cnt, inc,
        rte_memory_order_seq_cst);
}

static inline void
rte_atomic32_sub(rte_atomic32_t *v, int32_t dec)
{
    rte_atomic_fetch_sub_explicit((volatile __rte_atomic int32_t *)&v->cnt, dec,
        rte_memory_order_seq_cst);
}

static inline void
rte_atomic32_inc(rte_atomic32_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline void
rte_atomic32_inc(rte_atomic32_t *v)
{
    rte_atomic32_add(v, 1);
}
#endif

static inline void
rte_atomic32_dec(rte_atomic32_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline void
rte_atomic32_dec(rte_atomic32_t *v)
{
    rte_atomic32_sub(v,1);
}
#endif

static inline int32_t
rte_atomic32_add_return(rte_atomic32_t *v, int32_t inc)
{
    return rte_atomic_fetch_add_explicit((volatile __rte_atomic int32_t *)&v->cnt, inc,
        rte_memory_order_seq_cst) + inc;
}

static inline int32_t
rte_atomic32_sub_return(rte_atomic32_t *v, int32_t dec)
{
    return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int32_t *)&v->cnt, dec,
        rte_memory_order_seq_cst) - dec;
}

static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline int rte_atomic32_inc_and_test(rte_atomic32_t *v)
{
    return rte_atomic_fetch_add_explicit((volatile __rte_atomic int32_t *)&v->cnt, 1,
        rte_memory_order_seq_cst) + 1 == 0;
}
#endif

static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline int rte_atomic32_dec_and_test(rte_atomic32_t *v)
{
    return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int32_t *)&v->cnt, 1,
        rte_memory_order_seq_cst) - 1 == 0;
}
#endif

static inline int rte_atomic32_test_and_set(rte_atomic32_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline int rte_atomic32_test_and_set(rte_atomic32_t *v)
{
    return rte_atomic32_cmpset((volatile uint32_t *)&v->cnt, 0, 1);
}
#endif

static inline void rte_atomic32_clear(rte_atomic32_t *v)
{
    v->cnt = 0;
}

/*------------------------- 64 bit atomic operations -------------------------*/

static inline int
rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src);

#ifdef RTE_FORCE_INTRINSICS
static inline int
rte_atomic64_cmpset(volatile uint64_t *dst, uint64_t exp, uint64_t src)
{
    return __sync_bool_compare_and_swap(dst, exp, src);
}
#endif

static inline uint64_t
rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val);

#ifdef RTE_FORCE_INTRINSICS
static inline uint64_t
rte_atomic64_exchange(volatile uint64_t *dst, uint64_t val)
{
    return rte_atomic_exchange_explicit(dst, val, rte_memory_order_seq_cst);
}
#endif

typedef struct {
    volatile int64_t cnt;  
} rte_atomic64_t;

#define RTE_ATOMIC64_INIT(val) { (val) }

static inline void
rte_atomic64_init(rte_atomic64_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline void
rte_atomic64_init(rte_atomic64_t *v)
{
#ifdef __LP64__
    v->cnt = 0;
#else
    int success = 0;
    uint64_t tmp;

    while (success == 0) {
        tmp = v->cnt;
        success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
                                      tmp, 0);
    }
#endif
}
#endif

static inline int64_t
rte_atomic64_read(rte_atomic64_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline int64_t
rte_atomic64_read(rte_atomic64_t *v)
{
#ifdef __LP64__
    return v->cnt;
#else
    int success = 0;
    uint64_t tmp;

    while (success == 0) {
        tmp = v->cnt;
        /* replace the value by itself */
        success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
                                      tmp, tmp);
    }
    return tmp;
#endif
}
#endif

static inline void
rte_atomic64_set(rte_atomic64_t *v, int64_t new_value);

#ifdef RTE_FORCE_INTRINSICS
static inline void
rte_atomic64_set(rte_atomic64_t *v, int64_t new_value)
{
#ifdef __LP64__
    v->cnt = new_value;
#else
    int success = 0;
    uint64_t tmp;

    while (success == 0) {
        tmp = v->cnt;
        success = rte_atomic64_cmpset((volatile uint64_t *)&v->cnt,
                                      tmp, new_value);
    }
#endif
}
#endif

static inline void
rte_atomic64_add(rte_atomic64_t *v, int64_t inc);

#ifdef RTE_FORCE_INTRINSICS
static inline void
rte_atomic64_add(rte_atomic64_t *v, int64_t inc)
{
    rte_atomic_fetch_add_explicit((volatile __rte_atomic int64_t *)&v->cnt, inc,
        rte_memory_order_seq_cst);
}
#endif

static inline void
rte_atomic64_sub(rte_atomic64_t *v, int64_t dec);

#ifdef RTE_FORCE_INTRINSICS
static inline void
rte_atomic64_sub(rte_atomic64_t *v, int64_t dec)
{
    rte_atomic_fetch_sub_explicit((volatile __rte_atomic int64_t *)&v->cnt, dec,
        rte_memory_order_seq_cst);
}
#endif

static inline void
rte_atomic64_inc(rte_atomic64_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline void
rte_atomic64_inc(rte_atomic64_t *v)
{
    rte_atomic64_add(v, 1);
}
#endif

static inline void
rte_atomic64_dec(rte_atomic64_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline void
rte_atomic64_dec(rte_atomic64_t *v)
{
    rte_atomic64_sub(v, 1);
}
#endif

static inline int64_t
rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc);

#ifdef RTE_FORCE_INTRINSICS
static inline int64_t
rte_atomic64_add_return(rte_atomic64_t *v, int64_t inc)
{
    return rte_atomic_fetch_add_explicit((volatile __rte_atomic int64_t *)&v->cnt, inc,
        rte_memory_order_seq_cst) + inc;
}
#endif

static inline int64_t
rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec);

#ifdef RTE_FORCE_INTRINSICS
static inline int64_t
rte_atomic64_sub_return(rte_atomic64_t *v, int64_t dec)
{
    return rte_atomic_fetch_sub_explicit((volatile __rte_atomic int64_t *)&v->cnt, dec,
        rte_memory_order_seq_cst) - dec;
}
#endif

static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline int rte_atomic64_inc_and_test(rte_atomic64_t *v)
{
    return rte_atomic64_add_return(v, 1) == 0;
}
#endif

static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline int rte_atomic64_dec_and_test(rte_atomic64_t *v)
{
    return rte_atomic64_sub_return(v, 1) == 0;
}
#endif

static inline int rte_atomic64_test_and_set(rte_atomic64_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline int rte_atomic64_test_and_set(rte_atomic64_t *v)
{
    return rte_atomic64_cmpset((volatile uint64_t *)&v->cnt, 0, 1);
}
#endif

static inline void rte_atomic64_clear(rte_atomic64_t *v);

#ifdef RTE_FORCE_INTRINSICS
static inline void rte_atomic64_clear(rte_atomic64_t *v)
{
    rte_atomic64_set(v, 0);
}
#endif

#endif

/*------------------------ 128 bit atomic operations -------------------------*/

typedef struct __rte_aligned(16) {
    union {
        uint64_t val[2];
#ifdef RTE_ARCH_64
#ifndef RTE_TOOLCHAIN_MSVC
        __extension__ __int128 int128;
#endif
#endif
    };
} rte_int128_t;

#ifdef __DOXYGEN__

static inline int
rte_atomic128_cmp_exchange(rte_int128_t *dst,
               rte_int128_t *exp,
               const rte_int128_t *src,
               unsigned int weak,
               int success,
               int failure);

#endif /* __DOXYGEN__ */

#endif /* _RTE_ATOMIC_H_ */