rte_pmd_ifpga.h

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/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2021 Intel Corporation
 */
 
#ifndef _RTE_PMD_IFPGA_H_
#define _RTE_PMD_IFPGA_H_
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <stdint.h>
 
#define IFPGA_MAX_PORT_NUM   4
 
typedef struct {
    uint8_t b[16];
} rte_pmd_ifpga_uuid;
 
typedef struct {
    uint32_t num_ports;
    uint32_t boot_page;
    uint64_t bitstream_id;
    uint64_t bitstream_metadata;
    rte_pmd_ifpga_uuid pr_id;
    uint32_t bmc_version;
    uint32_t bmc_nios_version;
} rte_pmd_ifpga_common_prop;
 
typedef struct {
    rte_pmd_ifpga_uuid afu_id;
    uint32_t type;   /* AFU memory access control type */
} rte_pmd_ifpga_port_prop;
 
typedef struct {
    rte_pmd_ifpga_common_prop  common;
    rte_pmd_ifpga_port_prop    port[IFPGA_MAX_PORT_NUM];
} rte_pmd_ifpga_prop;
 
typedef struct {
    uint32_t num_retimers;
    uint32_t link_speed;
    uint32_t link_status;
} rte_pmd_ifpga_phy_info;
 
int
rte_pmd_ifpga_get_dev_id(const char *pci_addr, uint16_t *dev_id);
 
int
rte_pmd_ifpga_get_rsu_status(uint16_t dev_id, uint32_t *stat, uint32_t *prog);
 
int
rte_pmd_ifpga_set_rsu_status(uint16_t dev_id, uint32_t stat, uint32_t prog);
 
int
rte_pmd_ifpga_get_property(uint16_t dev_id, rte_pmd_ifpga_prop *prop);
 
int
rte_pmd_ifpga_get_phy_info(uint16_t dev_id, rte_pmd_ifpga_phy_info *info);
 
int
rte_pmd_ifpga_update_flash(uint16_t dev_id, const char *image,
    uint64_t *status);
 
int
rte_pmd_ifpga_stop_update(uint16_t dev_id, int force);
 
int
rte_pmd_ifpga_reboot_try(uint16_t dev_id);
 
int
rte_pmd_ifpga_reload(uint16_t dev_id, int type, int page);
 
int
rte_pmd_ifpga_partial_reconfigure(uint16_t dev_id, int port, const char *file);
 
void
rte_pmd_ifpga_cleanup(void);
 
#ifdef __cplusplus
}
#endif
 
#endif /* _RTE_PMD_IFPGA_H_ */