#include <stdint.h>
#include <memory.h>
#include "main.h"
#include "cfg_file.h"
uint32_t app_numa_mask = 0;
static uint32_t app_inited_port_mask = 0;
int app_pipe_to_profile[MAX_SCHED_SUBPORTS][MAX_SCHED_PIPES];
#define MAX_NAME_LEN 32
struct ring_conf ring_conf = {
.rx_size = APP_RX_DESC_DEFAULT,
.ring_size = APP_RING_SIZE,
.tx_size = APP_TX_DESC_DEFAULT,
};
struct burst_conf burst_conf = {
.rx_burst = MAX_PKT_RX_BURST,
.ring_burst = PKT_ENQUEUE,
.qos_dequeue = PKT_DEQUEUE,
.tx_burst = MAX_PKT_TX_BURST,
};
struct ring_thresh rx_thresh = {
.pthresh = RX_PTHRESH,
.hthresh = RX_HTHRESH,
.wthresh = RX_WTHRESH,
};
struct ring_thresh tx_thresh = {
.pthresh = TX_PTHRESH,
.hthresh = TX_HTHRESH,
.wthresh = TX_WTHRESH,
};
uint32_t nb_pfc;
const char *cfg_profile = NULL;
int mp_size = NB_MBUF;
struct flow_conf qos_conf[MAX_DATA_STREAMS];
.split_hdr_size = 0,
},
.txmode = {
},
};
static int
{
int ret;
uint16_t rx_size;
uint16_t tx_size;
if (app_inited_port_mask & (1u << portid))
return 0;
RTE_LOG(INFO, APP,
"Initializing port %"PRIu16
"... ", portid);
fflush(stdout);
if (ret != 0)
"Error during getting device (port %u) info: %s\n",
portid, strerror(-ret));
if (ret < 0)
"Cannot configure device: err=%d, port=%u\n",
ret, portid);
rx_size = ring_conf.rx_size;
tx_size = ring_conf.tx_size;
if (ret < 0)
"rte_eth_dev_adjust_nb_rx_tx_desc: err=%d,port=%u\n",
ret, portid);
ring_conf.rx_size = rx_size;
ring_conf.tx_size = tx_size;
fflush(stdout);
if (ret < 0)
"rte_eth_tx_queue_setup: err=%d, port=%u\n",
ret, portid);
fflush(stdout);
if (ret < 0)
"rte_eth_tx_queue_setup: err=%d, port=%u queue=%d\n",
ret, portid, 0);
if (ret < 0)
"rte_pmd_port_start: err=%d, port=%u\n",
ret, portid);
printf("done: ");
if (ret < 0)
"rte_eth_link_get: err=%d, port=%u: %s\n",
printf("%s\n", link_status_text);
if (ret != 0)
"rte_eth_promiscuous_enable: err=%s, port=%u\n",
app_inited_port_mask |= 1u << portid;
return 0;
}
static struct rte_sched_pipe_params pipe_profiles[MAX_SCHED_PIPE_PROFILES] = {
{
.tb_rate = 305175,
.tb_size = 1000000,
.tc_rate = {305175, 305175, 305175, 305175, 305175, 305175,
305175, 305175, 305175, 305175, 305175, 305175, 305175},
.tc_period = 40,
#ifdef RTE_SCHED_SUBPORT_TC_OV
.tc_ov_weight = 1,
#endif
.wrr_weights = {1, 1, 1, 1},
},
};
static struct rte_sched_subport_profile_params
subport_profile[MAX_SCHED_SUBPORT_PROFILES] = {
{
.tb_rate = 1250000000,
.tb_size = 1000000,
.tc_rate = {1250000000, 1250000000, 1250000000, 1250000000,
1250000000, 1250000000, 1250000000, 1250000000, 1250000000,
1250000000, 1250000000, 1250000000, 1250000000},
.tc_period = 10,
},
};
struct rte_sched_subport_params subport_params[MAX_SCHED_SUBPORTS] = {
{
.n_pipes_per_subport_enabled = 4096,
.qsize = {64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 64},
.pipe_profiles = pipe_profiles,
.n_pipe_profiles = sizeof(pipe_profiles) /
sizeof(struct rte_sched_pipe_params),
.n_max_pipe_profiles = MAX_SCHED_PIPE_PROFILES,
#ifdef RTE_SCHED_RED
.red_params = {
[0][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[0][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[0][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[1][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[1][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[1][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[2][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[2][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[2][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[3][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[3][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[3][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[4][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[4][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[4][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[5][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[5][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[5][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[6][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[6][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[6][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[7][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[7][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[7][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[8][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[8][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[8][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[9][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[9][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[9][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[10][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[10][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[10][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[11][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[11][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[11][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[12][0] = {.min_th = 48, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[12][1] = {.min_th = 40, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
[12][2] = {.min_th = 32, .max_th = 64, .maxp_inv = 10, .wq_log2 = 9},
},
#endif
},
};
.
name =
"port_scheduler_0",
.socket = 0,
.rate = 0,
.mtu = 6 + 6 + 4 + 4 + 2 + 1500,
.frame_overhead = RTE_SCHED_FRAME_OVERHEAD_DEFAULT,
.n_subports_per_port = 1,
.n_subport_profiles = 1,
.subport_profiles = subport_profile,
.n_max_subport_profiles = MAX_SCHED_SUBPORT_PROFILES,
.n_pipes_per_subport = MAX_SCHED_PIPES,
};
static struct rte_sched_port *
app_init_sched_port(uint32_t portid, uint32_t socketid)
{
static char port_name[32];
struct rte_sched_port *port = NULL;
uint32_t pipe, subport;
int err;
if (err < 0)
"rte_eth_link_get: err=%d, port=%u: %s\n",
port_params.
socket = socketid;
snprintf(port_name, sizeof(port_name), "port_%d", portid);
port_params.
name = port_name;
if (port == NULL){
rte_exit(EXIT_FAILURE,
"Unable to config sched port\n");
}
&subport_params[subport],
0);
if (err) {
rte_exit(EXIT_FAILURE,
"Unable to config sched " "subport %u, err=%d\n", subport, err);
}
uint32_t n_pipes_per_subport =
subport_params[subport].n_pipes_per_subport_enabled;
for (pipe = 0; pipe < n_pipes_per_subport; pipe++) {
if (app_pipe_to_profile[subport][pipe] != -1) {
app_pipe_to_profile[subport][pipe]);
if (err) {
rte_exit(EXIT_FAILURE,
"Unable to config sched pipe %u " "for profile %d, err=%d\n", pipe,
app_pipe_to_profile[subport][pipe], err);
}
}
}
}
return port;
}
static int
app_load_cfg_profile(const char *profile)
{
if (profile == NULL)
return 0;
if (file == NULL)
rte_exit(EXIT_FAILURE,
"Cannot load configuration profile %s\n", profile);
cfg_load_port(file, &port_params);
cfg_load_subport(file, subport_params);
cfg_load_subport_profile(file, subport_profile);
cfg_load_pipe(file, pipe_profiles);
return 0;
}
int app_init(void)
{
uint32_t i;
char ring_name[MAX_NAME_LEN];
char pool_name[MAX_NAME_LEN];
rte_exit(EXIT_FAILURE,
"No Ethernet port - bye\n");
if (app_load_cfg_profile(cfg_profile) != 0)
rte_exit(EXIT_FAILURE,
"Invalid configuration profile\n");
for(i = 0; i < nb_pfc; i++) {
snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].rx_core);
if (ring == NULL)
else
qos_conf[i].rx_ring = ring;
snprintf(ring_name, MAX_NAME_LEN, "ring-%u-%u", i, qos_conf[i].tx_core);
if (ring == NULL)
else
qos_conf[i].tx_ring = ring;
snprintf(pool_name, MAX_NAME_LEN, "mbuf_pool%u", i);
mp_size, burst_conf.rx_burst * 4, 0,
RTE_MBUF_DEFAULT_BUF_SIZE,
if (qos_conf[i].mbuf_pool == NULL)
rte_exit(EXIT_FAILURE,
"Cannot init mbuf pool for socket %u\n", i);
app_init_port(qos_conf[i].rx_port, qos_conf[i].mbuf_pool);
app_init_port(qos_conf[i].tx_port, qos_conf[i].mbuf_pool);
qos_conf[i].sched_port = app_init_sched_port(qos_conf[i].tx_port, socket);
}
RTE_LOG(INFO, APP,
"time stamp clock running at %" PRIu64
" Hz\n",
RTE_LOG(INFO, APP,
"Ring sizes: NIC RX = %u, Mempool = %d SW queue = %u," "NIC TX = %u\n", ring_conf.rx_size, mp_size, ring_conf.ring_size,
ring_conf.tx_size);
RTE_LOG(INFO, APP,
"Burst sizes: RX read = %hu, RX write = %hu,\n" " Worker read/QoS enqueue = %hu,\n"
" QoS dequeue = %hu, Worker write = %hu\n",
burst_conf.rx_burst, burst_conf.ring_burst, burst_conf.ring_burst,
burst_conf.qos_dequeue, burst_conf.tx_burst);
RTE_LOG(INFO, APP,
"NIC thresholds RX (p = %hhu, h = %hhu, w = %hhu)," "TX (p = %hhu, h = %hhu, w = %hhu)\n",
rx_thresh.pthresh, rx_thresh.hthresh, rx_thresh.wthresh,
tx_thresh.pthresh, tx_thresh.hthresh, tx_thresh.wthresh);
return 0;
}