rte_pmd_i40e.h

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/*-
 *   BSD LICENSE
 *
 *   Copyright (c) 2017 Intel Corporation. All rights reserved.
 *
 *   Redistribution and use in source and binary forms, with or without
 *   modification, are permitted provided that the following conditions
 *   are met:
 *
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in
 *       the documentation and/or other materials provided with the
 *       distribution.
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 *       contributors may be used to endorse or promote products derived
 *       from this software without specific prior written permission.
 *
 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _PMD_I40E_H_
#define _PMD_I40E_H_

#include <rte_ethdev.h>

enum rte_pmd_i40e_mb_event_rsp {
    RTE_PMD_I40E_MB_EVENT_NOOP_ACK,  
    RTE_PMD_I40E_MB_EVENT_NOOP_NACK, 
    RTE_PMD_I40E_MB_EVENT_PROCEED,  
    RTE_PMD_I40E_MB_EVENT_MAX       
};

struct rte_pmd_i40e_mb_event_param {
    uint16_t vfid;     
    uint16_t msg_type; 
    uint16_t retval;   
    void *msg;         
    uint16_t msglen;   
};

enum rte_pmd_i40e_package_op {
    RTE_PMD_I40E_PKG_OP_UNDEFINED = 0,
    RTE_PMD_I40E_PKG_OP_WR_ADD,   
    RTE_PMD_I40E_PKG_OP_WR_DEL, 
    RTE_PMD_I40E_PKG_OP_WR_ONLY, 
    RTE_PMD_I40E_PKG_OP_MAX = 32
};

enum rte_pmd_i40e_package_info {
    RTE_PMD_I40E_PKG_INFO_UNDEFINED = 0,
    RTE_PMD_I40E_PKG_INFO_GLOBAL_HEADER,
    RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES_SIZE,
    RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES,
    RTE_PMD_I40E_PKG_INFO_GLOBAL_MAX = 1024,
    RTE_PMD_I40E_PKG_INFO_HEADER,
    RTE_PMD_I40E_PKG_INFO_DEVID_NUM,
    RTE_PMD_I40E_PKG_INFO_DEVID_LIST,
    RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM,
    RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST,
    RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM,
    RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST,
    RTE_PMD_I40E_PKG_INFO_PTYPE_NUM,
    RTE_PMD_I40E_PKG_INFO_PTYPE_LIST,
    RTE_PMD_I40E_PKG_INFO_MAX = (int)0xFFFFFFFF
};

enum rte_pmd_i40e_queue_region_op {
    RTE_PMD_I40E_RSS_QUEUE_REGION_UNDEFINED,
    RTE_PMD_I40E_RSS_QUEUE_REGION_SET,
    RTE_PMD_I40E_RSS_QUEUE_REGION_FLOWTYPE_SET,
    RTE_PMD_I40E_RSS_QUEUE_REGION_USER_PRIORITY_SET,
    RTE_PMD_I40E_RSS_QUEUE_REGION_ALL_FLUSH_ON,
    RTE_PMD_I40E_RSS_QUEUE_REGION_ALL_FLUSH_OFF,
    RTE_PMD_I40E_RSS_QUEUE_REGION_INFO_GET,
    RTE_PMD_I40E_RSS_QUEUE_REGION_OP_MAX
};

#define RTE_PMD_I40E_DDP_NAME_SIZE     32
#define RTE_PMD_I40E_PCTYPE_MAX        64
#define RTE_PMD_I40E_REGION_MAX_NUM    8
#define RTE_PMD_I40E_MAX_USER_PRIORITY 8

struct rte_pmd_i40e_ddp_version {
    uint8_t major;
    uint8_t minor;
    uint8_t update;
    uint8_t draft;
};

struct rte_pmd_i40e_ddp_device_id {
    uint32_t vendor_dev_id;
    uint32_t sub_vendor_dev_id;
};

struct rte_pmd_i40e_profile_info {
    uint32_t track_id;
    struct rte_pmd_i40e_ddp_version version;
    uint8_t owner;
    uint8_t reserved[7];
    uint8_t name[RTE_PMD_I40E_DDP_NAME_SIZE];
};

#define RTE_PMD_I40E_DDP_OWNER_UNKNOWN 0xFF

struct rte_pmd_i40e_profile_list {
    uint32_t p_count;
    struct rte_pmd_i40e_profile_info p_info[1];
};

#define RTE_PMD_I40E_PROTO_NUM 6
#define RTE_PMD_I40E_PROTO_UNUSED 0xFF

struct rte_pmd_i40e_proto_info {
    uint8_t proto_id;
    char name[RTE_PMD_I40E_DDP_NAME_SIZE];
};

struct rte_pmd_i40e_ptype_info {
    uint8_t ptype_id;
    uint8_t protocols[RTE_PMD_I40E_PROTO_NUM];
};

#define RTE_PMD_I40E_PTYPE_USER_DEFINE_MASK 0x80000000

struct rte_pmd_i40e_ptype_mapping {
    uint16_t hw_ptype; 
    uint32_t sw_ptype; 
};

struct rte_pmd_i40e_queue_region_conf {
    uint8_t region_id;
    uint8_t hw_flowtype;
    uint8_t queue_start_index;
    uint8_t queue_num;
    uint8_t user_priority;
};

/* queue region info */
struct rte_pmd_i40e_queue_region_info {
    uint8_t region_id;
    uint8_t queue_start_index;
    uint8_t queue_num;
    uint8_t user_priority_num;
    uint8_t user_priority[RTE_PMD_I40E_MAX_USER_PRIORITY];
    uint8_t flowtype_num;
    uint8_t hw_flowtype[RTE_PMD_I40E_PCTYPE_MAX];
};

struct rte_pmd_i40e_queue_regions {
    uint16_t queue_region_number;
    struct rte_pmd_i40e_queue_region_info
        region[RTE_PMD_I40E_REGION_MAX_NUM];
};

enum rte_pmd_i40e_pkt_template_behavior {
    RTE_PMD_I40E_PKT_TEMPLATE_ACCEPT,
    RTE_PMD_I40E_PKT_TEMPLATE_REJECT,
    RTE_PMD_I40E_PKT_TEMPLATE_PASSTHRU,
};

enum rte_pmd_i40e_pkt_template_status {
    RTE_PMD_I40E_PKT_TEMPLATE_NO_REPORT_STATUS,
    RTE_PMD_I40E_PKT_TEMPLATE_REPORT_ID,
    RTE_PMD_I40E_PKT_TEMPLATE_REPORT_ID_FLEX_4,
    RTE_PMD_I40E_PKT_TEMPLATE_REPORT_FLEX_8,
};

struct rte_pmd_i40e_pkt_template_action {
    uint16_t rx_queue;
    enum rte_pmd_i40e_pkt_template_behavior behavior;
    enum rte_pmd_i40e_pkt_template_status report_status;
    uint8_t flex_off;
};

struct rte_pmd_i40e_pkt_template_input {
    uint16_t pctype;
    void *packet;
    uint32_t length;
};

struct rte_pmd_i40e_pkt_template_conf {
    struct rte_pmd_i40e_pkt_template_input input;
    struct rte_pmd_i40e_pkt_template_action action;
    uint32_t soft_id;
};

int rte_pmd_i40e_flow_add_del_packet_template(
            uint16_t port,
            const struct rte_pmd_i40e_pkt_template_conf *conf,
            uint8_t add);

int rte_pmd_i40e_ping_vfs(uint16_t port, uint16_t vf);

int rte_pmd_i40e_set_vf_mac_anti_spoof(uint16_t port,
                       uint16_t vf_id,
                       uint8_t on);

int rte_pmd_i40e_set_vf_vlan_anti_spoof(uint16_t port,
                    uint16_t vf_id,
                    uint8_t on);

int rte_pmd_i40e_set_tx_loopback(uint16_t port,
                 uint8_t on);

int rte_pmd_i40e_set_vf_unicast_promisc(uint16_t port,
                    uint16_t vf_id,
                    uint8_t on);

int rte_pmd_i40e_set_vf_multicast_promisc(uint16_t port,
                      uint16_t vf_id,
                      uint8_t on);

int rte_pmd_i40e_set_vf_mac_addr(uint16_t port, uint16_t vf_id,
                 struct ether_addr *mac_addr);

int
rte_pmd_i40e_set_vf_vlan_stripq(uint16_t port, uint16_t vf, uint8_t on);

int rte_pmd_i40e_set_vf_vlan_insert(uint16_t port, uint16_t vf_id,
                    uint16_t vlan_id);

int rte_pmd_i40e_set_vf_broadcast(uint16_t port, uint16_t vf_id,
                  uint8_t on);

int rte_pmd_i40e_set_vf_vlan_tag(uint16_t port, uint16_t vf_id, uint8_t on);

int rte_pmd_i40e_set_vf_vlan_filter(uint16_t port, uint16_t vlan_id,
                    uint64_t vf_mask, uint8_t on);

int rte_pmd_i40e_get_vf_stats(uint16_t port,
                  uint16_t vf_id,
                  struct rte_eth_stats *stats);

int rte_pmd_i40e_reset_vf_stats(uint16_t port,
                uint16_t vf_id);

int rte_pmd_i40e_set_vf_max_bw(uint16_t port,
                   uint16_t vf_id,
                   uint32_t bw);

int rte_pmd_i40e_set_vf_tc_bw_alloc(uint16_t port,
                    uint16_t vf_id,
                    uint8_t tc_num,
                    uint8_t *bw_weight);

int rte_pmd_i40e_set_vf_tc_max_bw(uint16_t port,
                  uint16_t vf_id,
                  uint8_t tc_no,
                  uint32_t bw);

int rte_pmd_i40e_set_tc_strict_prio(uint16_t port, uint8_t tc_map);

int rte_pmd_i40e_process_ddp_package(uint16_t port, uint8_t *buff,
                     uint32_t size,
                     enum rte_pmd_i40e_package_op op);

int rte_pmd_i40e_get_ddp_info(uint8_t *pkg, uint32_t pkg_size,
                     uint8_t *info, uint32_t size,
                     enum rte_pmd_i40e_package_info type);

int rte_pmd_i40e_get_ddp_list(uint16_t port, uint8_t *buff, uint32_t size);

int rte_pmd_i40e_ptype_mapping_update(
            uint16_t port,
            struct rte_pmd_i40e_ptype_mapping *mapping_items,
            uint16_t count,
            uint8_t exclusive);

int rte_pmd_i40e_ptype_mapping_reset(uint16_t port);

int rte_pmd_i40e_ptype_mapping_get(
            uint16_t port,
            struct rte_pmd_i40e_ptype_mapping *mapping_items,
            uint16_t size,
            uint16_t *count,
            uint8_t valid_only);

int rte_pmd_i40e_ptype_mapping_replace(uint16_t port,
                       uint32_t target,
                       uint8_t mask,
                       uint32_t pkt_type);

int rte_pmd_i40e_add_vf_mac_addr(uint16_t port, uint16_t vf_id,
                 struct ether_addr *mac_addr);

#define RTE_PMD_I40E_PCTYPE_MAX     64
#define RTE_PMD_I40E_FLOW_TYPE_MAX  64

struct rte_pmd_i40e_flow_type_mapping {
    uint16_t flow_type; 
    uint64_t pctype;    
};

int rte_pmd_i40e_flow_type_mapping_update(
            uint16_t port,
            struct rte_pmd_i40e_flow_type_mapping *mapping_items,
            uint16_t count,
            uint8_t exclusive);

int rte_pmd_i40e_flow_type_mapping_get(
            uint16_t port,
            struct rte_pmd_i40e_flow_type_mapping *mapping_items);

int rte_pmd_i40e_flow_type_mapping_reset(uint16_t port);

int rte_pmd_i40e_query_vfid_by_mac(uint16_t port,
                    const struct ether_addr *vf_mac);

int rte_pmd_i40e_rss_queue_region_conf(uint16_t port_id,
            enum rte_pmd_i40e_queue_region_op op_type, void *arg);

#endif /* _PMD_I40E_H_ */