DPDK  2.1.0
rte_eth_ctrl.h
Go to the documentation of this file.
1 /*-
2  * BSD LICENSE
3  *
4  * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  *
11  * * Redistributions of source code must retain the above copyright
12  * notice, this list of conditions and the following disclaimer.
13  * * Redistributions in binary form must reproduce the above copyright
14  * notice, this list of conditions and the following disclaimer in
15  * the documentation and/or other materials provided with the
16  * distribution.
17  * * Neither the name of Intel Corporation nor the names of its
18  * contributors may be used to endorse or promote products derived
19  * from this software without specific prior written permission.
20  *
21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32  */
33 
34 #ifndef _RTE_ETH_CTRL_H_
35 #define _RTE_ETH_CTRL_H_
36 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
49 /*
50  * A packet can be identified by hardware as different flow types. Different
51  * NIC hardwares may support different flow types.
52  * Basically, the NIC hardware identifies the flow type as deep protocol as
53  * possible, and exclusively. For example, if a packet is identified as
54  * 'RTE_ETH_FLOW_NONFRAG_IPV4_TCP', it will not be any of other flow types,
55  * though it is an actual IPV4 packet.
56  * Note that the flow types are used to define RSS offload types in
57  * rte_ethdev.h.
58  */
59 #define RTE_ETH_FLOW_UNKNOWN 0
60 #define RTE_ETH_FLOW_RAW 1
61 #define RTE_ETH_FLOW_IPV4 2
62 #define RTE_ETH_FLOW_FRAG_IPV4 3
63 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4
64 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5
65 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6
66 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7
67 #define RTE_ETH_FLOW_IPV6 8
68 #define RTE_ETH_FLOW_FRAG_IPV6 9
69 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10
70 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11
71 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12
72 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13
73 #define RTE_ETH_FLOW_L2_PAYLOAD 14
74 #define RTE_ETH_FLOW_IPV6_EX 15
75 #define RTE_ETH_FLOW_IPV6_TCP_EX 16
76 #define RTE_ETH_FLOW_IPV6_UDP_EX 17
77 #define RTE_ETH_FLOW_MAX 18
78 
83  RTE_ETH_FILTER_NONE = 0,
84  RTE_ETH_FILTER_MACVLAN,
85  RTE_ETH_FILTER_ETHERTYPE,
86  RTE_ETH_FILTER_FLEXIBLE,
87  RTE_ETH_FILTER_SYN,
88  RTE_ETH_FILTER_NTUPLE,
89  RTE_ETH_FILTER_TUNNEL,
90  RTE_ETH_FILTER_FDIR,
91  RTE_ETH_FILTER_HASH,
92  RTE_ETH_FILTER_MAX
93 };
94 
109  RTE_ETH_FILTER_OP_MAX
110 };
111 
121 };
122 
127  uint8_t is_vf;
128  uint16_t dst_id;
130  struct ether_addr mac_addr;
131 };
132 
137 #define RTE_ETHTYPE_FLAGS_MAC 0x0001
138 #define RTE_ETHTYPE_FLAGS_DROP 0x0002
145 struct rte_eth_ethertype_filter {
146  struct ether_addr mac_addr;
147  uint16_t ether_type;
148  uint16_t flags;
149  uint16_t queue;
150 };
151 
152 #define RTE_FLEX_FILTER_MAXLEN 128
153 #define RTE_FLEX_FILTER_MASK_SIZE \
154  (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
155 
163  uint16_t len;
167  uint8_t priority;
168  uint16_t queue;
169 };
170 
177  uint8_t hig_pri;
179  uint16_t queue;
180 };
181 
186 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
187 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
188 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
189 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
190 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
191 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
193 #define RTE_5TUPLE_FLAGS ( \
194  RTE_NTUPLE_FLAGS_DST_IP | \
195  RTE_NTUPLE_FLAGS_SRC_IP | \
196  RTE_NTUPLE_FLAGS_DST_PORT | \
197  RTE_NTUPLE_FLAGS_SRC_PORT | \
198  RTE_NTUPLE_FLAGS_PROTO)
199 
200 #define RTE_2TUPLE_FLAGS ( \
201  RTE_NTUPLE_FLAGS_DST_PORT | \
202  RTE_NTUPLE_FLAGS_PROTO)
203 
204 #define TCP_URG_FLAG 0x20
205 #define TCP_ACK_FLAG 0x10
206 #define TCP_PSH_FLAG 0x08
207 #define TCP_RST_FLAG 0x04
208 #define TCP_SYN_FLAG 0x02
209 #define TCP_FIN_FLAG 0x01
210 #define TCP_FLAG_ALL 0x3F
211 
218  uint16_t flags;
219  uint32_t dst_ip;
220  uint32_t dst_ip_mask;
221  uint32_t src_ip;
222  uint32_t src_ip_mask;
223  uint16_t dst_port;
224  uint16_t dst_port_mask;
225  uint16_t src_port;
226  uint16_t src_port_mask;
227  uint8_t proto;
228  uint8_t proto_mask;
232  uint8_t tcp_flags;
233  uint16_t priority;
235  uint16_t queue;
236 };
237 
242  RTE_TUNNEL_TYPE_NONE = 0,
243  RTE_TUNNEL_TYPE_VXLAN,
244  RTE_TUNNEL_TYPE_GENEVE,
245  RTE_TUNNEL_TYPE_TEREDO,
246  RTE_TUNNEL_TYPE_NVGRE,
247  RTE_TUNNEL_TYPE_MAX,
248 };
249 
253 #define ETH_TUNNEL_FILTER_OMAC 0x01
254 #define ETH_TUNNEL_FILTER_OIP 0x02
255 #define ETH_TUNNEL_FILTER_TENID 0x04
256 #define ETH_TUNNEL_FILTER_IMAC 0x08
257 #define ETH_TUNNEL_FILTER_IVLAN 0x10
258 #define ETH_TUNNEL_FILTER_IIP 0x20
260 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
261  ETH_TUNNEL_FILTER_IVLAN)
262 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
263  ETH_TUNNEL_FILTER_IVLAN | \
264  ETH_TUNNEL_FILTER_TENID)
265 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
266  ETH_TUNNEL_FILTER_TENID)
267 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
268  ETH_TUNNEL_FILTER_TENID | \
269  ETH_TUNNEL_FILTER_IMAC)
270 
277 };
278 
285  uint16_t inner_vlan;
287  union {
288  uint32_t ipv4_addr;
289  uint32_t ipv6_addr[4];
290  } ip_addr;
292  uint16_t filter_type;
294  uint32_t tenant_id;
295  uint16_t queue_id;
296 };
297 
298 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
303 struct rte_eth_l2_flow {
304  uint16_t ether_type;
305 };
306 
311  uint32_t src_ip;
312  uint32_t dst_ip;
313 };
314 
320  uint16_t src_port;
321  uint16_t dst_port;
322 };
323 
329  uint16_t src_port;
330  uint16_t dst_port;
331 };
332 
338 #ifdef RTE_NEXT_ABI
339  uint16_t src_port;
340  uint16_t dst_port;
341 #endif
342  uint32_t verify_tag;
343 };
344 
349  uint32_t src_ip[4];
350  uint32_t dst_ip[4];
351 };
352 
358  uint16_t src_port;
359  uint16_t dst_port;
360 };
361 
367  uint16_t src_port;
368  uint16_t dst_port;
369 };
370 
376 #ifdef RTE_NEXT_ABI
377  uint16_t src_port;
378  uint16_t dst_port;
379 #endif
380  uint32_t verify_tag;
381 };
382 
387  struct rte_eth_l2_flow l2_flow;
388  struct rte_eth_udpv4_flow udp4_flow;
389  struct rte_eth_tcpv4_flow tcp4_flow;
390  struct rte_eth_sctpv4_flow sctp4_flow;
391  struct rte_eth_ipv4_flow ip4_flow;
392  struct rte_eth_udpv6_flow udp6_flow;
393  struct rte_eth_tcpv6_flow tcp6_flow;
394  struct rte_eth_sctpv6_flow sctp6_flow;
395  struct rte_eth_ipv6_flow ipv6_flow;
396 };
397 
402  uint16_t vlan_tci;
403  uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
405 };
406 
411  uint16_t flow_type;
416 };
417 
422  RTE_ETH_FDIR_ACCEPT = 0,
423  RTE_ETH_FDIR_REJECT,
424 };
425 
435 };
436 
441  uint16_t rx_queue;
444  uint8_t flex_off;
448 };
449 
456  uint32_t soft_id;
460 };
461 
467  uint16_t vlan_tci_mask;
468  struct rte_eth_ipv4_flow ipv4_mask;
469  struct rte_eth_ipv6_flow ipv6_mask;
470  uint16_t src_port_mask;
471  uint16_t dst_port_mask;
472 };
473 
478  RTE_ETH_PAYLOAD_UNKNOWN = 0,
479  RTE_ETH_RAW_PAYLOAD,
480  RTE_ETH_L2_PAYLOAD,
481  RTE_ETH_L3_PAYLOAD,
482  RTE_ETH_L4_PAYLOAD,
483  RTE_ETH_PAYLOAD_MAX = 8,
484 };
485 
492  uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN];
497 };
498 
504  uint16_t flow_type;
505  uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN];
507 };
508 
514  uint16_t nb_payloads;
515  uint16_t nb_flexmasks;
516  struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
518  struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
520 };
521 
529 };
530 
531 #define UINT32_BIT (CHAR_BIT * sizeof(uint32_t))
532 #define RTE_FLOW_MASK_ARRAY_SIZE \
533  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)
534 
544  struct rte_eth_fdir_masks mask;
547  uint32_t guarant_spc;
548  uint32_t best_spc;
550  uint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
551  uint32_t max_flexpayload;
567 };
568 
574  uint32_t collision;
575  uint32_t free;
576  uint32_t maxhash;
579  uint32_t maxlen;
580  uint64_t add;
581  uint64_t remove;
582  uint64_t f_add;
583  uint64_t f_remove;
584  uint32_t guarant_cnt;
585  uint32_t best_cnt;
586 };
587 
597  RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
602  RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
603 };
604 
609  RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
612  RTE_ETH_HASH_FUNCTION_MAX,
613 };
614 
615 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \
616  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)
617 
629  uint32_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
631  uint32_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
632 };
633 
641  union {
643  uint8_t enable;
646  } info;
647 };
648 
649 #ifdef __cplusplus
650 }
651 #endif
652 
653 #endif /* _RTE_ETH_CTRL_H_ */