DPDK 26.11.0-rc2
rte_pmd_cnxk.h
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1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2022 Marvell.
3 */
4
11#ifndef _PMD_CNXK_H_
12#define _PMD_CNXK_H_
13
14#include <rte_compat.h>
15#include <rte_ethdev.h>
16#include <rte_ether.h>
17#include <rte_security.h>
18
48};
49
60};
61
65 uint64_t enc_pkts;
67 uint64_t enc_bytes;
69 uint64_t dec_pkts;
71 uint64_t dec_bytes;
72};
73
74struct rte_pmd_cnxk_sec_action {
76 uint32_t sa_index;
78 bool sa_xor;
80 uint16_t sa_hi, sa_lo;
85 bool is_non_inp;
90 uint16_t profile_id;
94 bool use_custom_profile;
95};
96
97#define RTE_PMD_CNXK_CTX_MAX_CKEY_LEN 32
98#define RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN 128
99
101#define RTE_PMD_CNXK_AR_WIN_SIZE_MIN 64
102#define RTE_PMD_CNXK_AR_WIN_SIZE_MAX 4096
103#define RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 5
104
106#define RTE_PMD_CNXK_AR_WINBITS_SZ (RTE_ALIGN_CEIL(RTE_PMD_CNXK_AR_WIN_SIZE_MAX, 64) / 64)
107
110 struct {
112 uint32_t dst_addr;
114 uint32_t src_addr;
115 } ipv4;
116 struct {
118 uint8_t src_addr[16];
120 uint8_t dst_addr[16];
121 } ipv6;
122};
123
127 uint64_t ar_base;
131 uint64_t hard_life;
133 uint64_t soft_life;
135 uint64_t mib_octs;
137 uint64_t mib_pkts;
140};
141
144 uint64_t u64[2];
146 uint8_t iv_dbg[16];
147 struct {
149 uint8_t iv_dbg1[4];
151 uint8_t salt[4];
152
153 uint32_t rsvd;
155 uint8_t iv_dbg2[4];
156 } s;
157};
158
161 union {
162 struct {
163 uint64_t reserved_0_2 : 3;
164 uint64_t address : 57;
165 uint64_t mode : 4;
166 } s;
167 uint64_t u64;
168 } err_ctl;
169
170 uint64_t esn_val;
171 uint64_t hard_life;
172 uint64_t soft_life;
173 uint64_t mib_octs;
174 uint64_t mib_pkts;
175};
176
182 union {
183 struct {
185 uint64_t ar_win : 3;
187 uint64_t hard_life_dec : 1;
189 uint64_t soft_life_dec : 1;
190
192 uint64_t count_glb_octets : 1;
194 uint64_t count_glb_pkts : 1;
196 uint64_t count_mib_bytes : 1;
197
199 uint64_t count_mib_pkts : 1;
201 uint64_t hw_ctx_off : 7;
202
204 uint64_t ctx_id : 16;
205
207 uint64_t orig_pkt_fabs : 1;
209 uint64_t orig_pkt_free : 1;
211 uint64_t pkind : 6;
212
213 uint64_t rsvd0 : 1;
215 uint64_t et_ovrwr : 1;
217 uint64_t pkt_output : 2;
219 uint64_t pkt_format : 1;
221 uint64_t defrag_opt : 2;
223 uint64_t x2p_dst : 1;
224
226 uint64_t ctx_push_size : 7;
227 uint64_t rsvd1 : 1;
228
230 uint64_t ctx_hdr_size : 2;
232 uint64_t aop_valid : 1;
233 uint64_t rsvd2 : 1;
235 uint64_t ctx_size : 4;
236 } s;
237 uint64_t u64;
238 } w0;
239
241 union {
242 struct {
244 uint64_t orig_pkt_aura : 20;
245 uint64_t rsvd3 : 4;
247 uint64_t orig_pkt_foff : 8;
249 uint64_t cookie : 32;
250 } s;
251 uint64_t u64;
252 } w1;
253
255 union {
256 struct {
258 uint64_t valid : 1;
260 uint64_t dir : 1;
261 uint64_t rsvd11 : 1;
262 uint64_t rsvd4 : 1;
264 uint64_t ipsec_mode : 1;
266 uint64_t ipsec_protocol : 1;
268 uint64_t aes_key_len : 2;
269
271 uint64_t enc_type : 3;
273 uint64_t life_unit : 1;
275 uint64_t auth_type : 4;
276
278 uint64_t encap_type : 2;
280 uint64_t et_ovrwr_ddr_en : 1;
282 uint64_t esn_en : 1;
284 uint64_t tport_l4_incr_csum : 1;
286 uint64_t ip_hdr_verify : 2;
288 uint64_t udp_ports_verify : 1;
289
291 uint64_t l3hdr_on_err : 1;
292 uint64_t rsvd6 : 6;
293 uint64_t rsvd12 : 1;
294
296 uint64_t spi : 32;
297 } s;
298 uint64_t u64;
299 } w2;
300
302 uint64_t rsvd7;
303
305 uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN];
306
308 union {
309 struct {
310 uint32_t rsvd8;
312 uint8_t salt[4];
313 } s;
314 uint64_t u64;
315 } w8;
316 uint64_t rsvd9;
317
319 union {
320 struct {
321 uint64_t rsvd10 : 32;
323 uint64_t udp_src_port : 16;
325 uint64_t udp_dst_port : 16;
326 } s;
327 uint64_t u64;
329
332
334 uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN];
335
338};
339
341#define RTE_PMD_CNXK_IPSEC_INB_MSNS_SPACES 4
342
344#define RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_BITS 1024
345
347#define RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_BYTES (RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_BITS / 8)
348
350#define RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_U64 \
351 (RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_BYTES / sizeof(uint64_t))
352
356 uint64_t ar_base;
358 uint64_t ar_valid;
359};
360
366struct __rte_aligned(32) rte_pmd_cnxk_ipsec_inb_ctx_msns_reg {
370 uint64_t hard_life;
372 uint64_t soft_life;
374 uint64_t mib_octs;
376 uint64_t mib_pkts;
378 uint64_t ar_winbits[RTE_PMD_CNXK_IPSEC_INB_MSNS_SPACES]
380};
381
383#define RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_SZ 1024
384
386#define RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_OFF \
387 RTE_ALIGN_CEIL(offsetof(struct rte_pmd_cnxk_ipsec_inb_sa, ctx), 32)
388
390#define RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_ALIGN_PAD \
391 (RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_OFF - offsetof(struct rte_pmd_cnxk_ipsec_inb_sa, ctx))
392
394#define RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_PUSH_SZ(hw_ctx_off_words) (hw_ctx_off_words)
395
404 union {
405 struct {
406 uint64_t ar_win : 3;
407 uint64_t hard_life_dec : 1;
408 uint64_t soft_life_dec : 1;
409 uint64_t count_glb_octets : 1;
410 uint64_t count_glb_pkts : 1;
411 uint64_t count_mib_bytes : 1;
412 uint64_t count_mib_pkts : 1;
413 uint64_t hw_ctx_off : 7;
414 uint64_t ctx_id : 16;
415 uint64_t orig_pkt_fabs : 1;
416 uint64_t orig_pkt_free : 1;
417 uint64_t pkind : 6;
418 uint64_t rsvd0 : 1;
419 uint64_t et_ovrwr : 1;
420 uint64_t pkt_output : 2;
421 uint64_t pkt_format : 1;
422 uint64_t defrag_opt : 2;
423 uint64_t x2p_dst : 1;
424 uint64_t ctx_push_size : 7;
425 uint64_t rsvd1 : 1;
426 uint64_t ctx_hdr_size : 2;
427 uint64_t aop_valid : 1;
428 uint64_t rsvd2 : 1;
429 uint64_t ctx_size : 4;
430 } s;
431 uint64_t u64;
432 } w0;
433
435 union {
436 struct {
437 uint64_t orig_pkt_aura : 20;
438 uint64_t rsvd3 : 4;
439 uint64_t orig_pkt_foff : 8;
440 uint64_t cookie : 32;
441 } s;
442 uint64_t u64;
443 } w1;
444
446 union {
447 struct {
448 uint64_t valid : 1;
449 uint64_t dir : 1;
450 uint64_t rsvd11 : 1;
451 uint64_t rsvd4 : 1;
452 uint64_t ipsec_mode : 1;
453 uint64_t ipsec_protocol : 1;
454 uint64_t aes_key_len : 2;
455 uint64_t enc_type : 3;
456 uint64_t life_unit : 1;
457 uint64_t auth_type : 4;
458 uint64_t encap_type : 2;
459 uint64_t et_ovrwr_ddr_en : 1;
460 uint64_t esn_en : 1;
461 uint64_t tport_l4_incr_csum : 1;
462 uint64_t ip_hdr_verify : 2;
463 uint64_t udp_ports_verify : 1;
464 uint64_t l3hdr_on_err : 1;
465 uint64_t rsvd6 : 6;
466 uint64_t rsvd12 : 1;
467 uint64_t spi : 32;
468 } s;
469 uint64_t u64;
470 } w2;
471
473 uint64_t rsvd7;
474
476 uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN];
477
479 union {
480 struct {
481 uint32_t rsvd8;
482 uint8_t salt[4];
483 } s;
484 uint64_t u64;
485 } w8;
486 uint64_t rsvd9;
487
489 union {
490 struct {
491 uint64_t rsvd10 : 32;
492 uint64_t udp_src_port : 16;
493 uint64_t udp_dst_port : 16;
494 } s;
495 uint64_t u64;
497
500
502 uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN];
503
506
508 struct rte_pmd_cnxk_ipsec_inb_ctx_msns_reg ctx;
509
512 sizeof(struct rte_pmd_cnxk_ipsec_inb_ctx_msns_reg)];
513};
514
516 "rte_pmd_cnxk_ipsec_inb_msns_sa must be 1KB");
517static_assert(RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_ALIGN_PAD == 8, "msns_sa ctx align pad must be 8B");
518static_assert((offsetof(struct rte_pmd_cnxk_ipsec_inb_msns_sa, ctx) % 32) == 0,
519 "msns_sa ctx must be 32-byte aligned");
520static_assert(offsetof(struct rte_pmd_cnxk_ipsec_inb_msns_sa, ctx) ==
522 "msns_sa ctx must start at Word32");
523static_assert((offsetof(struct rte_pmd_cnxk_ipsec_inb_msns_sa, ctx) / 8) <= 32,
524 "msns_sa hw_ctx_off must be <= 32 without CTX caching");
525static_assert((offsetof(struct rte_pmd_cnxk_ipsec_inb_msns_sa, ctx.ar_winbits) % 32) == 0,
526 "msns_sa ar_winbits must be 32-byte aligned");
527static_assert(offsetof(struct rte_pmd_cnxk_ipsec_inb_msns_sa, w1) ==
529 "msns_sa w1 offset must match inb_sa");
530static_assert(offsetof(struct rte_pmd_cnxk_ipsec_inb_msns_sa, w2) ==
532 "msns_sa w2 offset must match inb_sa");
533
536
538#define RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_SZ_ALIGN RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_SZ
539
541#define RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_WR_SZ offsetof(struct rte_pmd_cnxk_ipsec_inb_msns_sa, rsvd)
542
548 union {
549 struct {
551 uint64_t esn_en : 1;
553 uint64_t ip_id : 1;
554 uint64_t rsvd0 : 1;
556 uint64_t hard_life_dec : 1;
558 uint64_t soft_life_dec : 1;
559
561 uint64_t count_glb_octets : 1;
563 uint64_t count_glb_pkts : 1;
565 uint64_t count_mib_bytes : 1;
566
568 uint64_t count_mib_pkts : 1;
570 uint64_t hw_ctx_off : 7;
571
573 uint64_t ctx_id : 16;
574 uint64_t rsvd1 : 16;
575
577 uint64_t ctx_push_size : 7;
578 uint64_t rsvd2 : 1;
579
581 uint64_t ctx_hdr_size : 2;
583 uint64_t aop_valid : 1;
584 uint64_t rsvd3 : 1;
586 uint64_t ctx_size : 4;
587 } s;
588 uint64_t u64;
589 } w0;
590
592 union {
593 struct {
594 uint64_t rsvd4 : 32;
596 uint64_t cookie : 32;
597 } s;
598 uint64_t u64;
599 } w1;
600
602 union {
603 struct {
605 uint64_t valid : 1;
607 uint64_t dir : 1;
608 uint64_t rsvd11 : 1;
609 uint64_t rsvd5 : 1;
611 uint64_t ipsec_mode : 1;
613 uint64_t ipsec_protocol : 1;
614
616 uint64_t aes_key_len : 2;
617
619 uint64_t enc_type : 3;
621 uint64_t life_unit : 1;
623 uint64_t auth_type : 4;
624
626 uint64_t encap_type : 2;
630 uint64_t dscp_src : 1;
632 uint64_t iv_src : 2;
634 uint64_t ipid_gen : 1;
635 uint64_t rsvd6 : 1;
636
637 uint64_t rsvd7 : 7;
638 uint64_t rsvd12 : 1;
639
641 uint64_t spi : 32;
642 } s;
643 uint64_t u64;
644 } w2;
645
647 uint64_t rsvd8;
648
650 uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN];
651
654
656 union {
657 struct {
658 uint64_t rsvd9 : 4;
661
663 uint64_t dscp : 6;
664 uint64_t rsvd10 : 2;
665
667 uint64_t udp_dst_port : 16;
668
670 uint64_t udp_src_port : 16;
671 } s;
672 uint64_t u64;
674
677
679 uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN];
680
683};
684
693};
694
700 uint64_t compcode : 7;
702 uint64_t doneint : 1;
704 uint64_t uc_compcode : 8;
706 uint64_t rlen : 16;
708 uint64_t spi : 32;
709
711 uint64_t esn;
712 } cn10k;
713
717 uint64_t compcode : 7;
719 uint64_t doneint : 1;
721 uint64_t uc_compcode : 8;
723 uint64_t rlen : 16;
725 uint64_t spi : 32;
726
728 uint64_t esn;
729 } cn20k;
730
734 uint64_t compcode : 8;
736 uint64_t uc_compcode : 8;
738 uint64_t doneint : 1;
739 uint64_t reserved_17_63 : 47;
740
741 uint64_t reserved_64_127;
742 } cn9k;
743
745 uint64_t u64[2];
746};
747
753 uint16_t param1;
757 uint16_t param2;
758};
759
765struct rte_pmd_cnxk_inl_dev_q;
766
784__rte_experimental
785int rte_pmd_cnxk_hw_sa_read(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data,
786 uint32_t len, bool inb);
804__rte_experimental
805int rte_pmd_cnxk_hw_sa_write(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data,
806 uint32_t len, bool inb);
807
822__rte_experimental
824
838__rte_experimental
840
852__rte_experimental
854 uint16_t profile_id);
855
869__rte_experimental
870int rte_pmd_cnxk_sa_flush(uint16_t portid, union rte_pmd_cnxk_ipsec_hw_sa *sess, bool inb);
871
879__rte_experimental
880struct rte_pmd_cnxk_inl_dev_q *rte_pmd_cnxk_inl_dev_qptr_get(void);
881
895__rte_experimental
896uint16_t rte_pmd_cnxk_inl_dev_submit(struct rte_pmd_cnxk_inl_dev_q *qptr, void *inst,
897 uint16_t nb_inst);
898
915__rte_experimental
917 struct rte_pmd_cnxk_cpt_q_stats *stats, uint16_t idx);
918
928__rte_experimental
930
938 uint64_t ltype_mask;
940 uint64_t ltype_match;
942 uint64_t lid;
946 uint64_t gen_offset;
948 uint64_t gen_nz;
950 uint64_t cpt_l3_lid;
952 uint64_t flags_mask;
954 uint64_t flags_match;
956 uint64_t match_oipv4;
958 uint64_t match_oipv6;
960 uint64_t oiplen_ena;
962 uint64_t inline_shift;
963};
964
971 uint64_t param2;
973 uint64_t param1;
975 uint64_t opcode;
977 uint64_t egrp;
979 uint64_t ctx_val;
980};
981
988 uint64_t len_l;
990 uint64_t bitpos_l;
992 uint64_t len_m;
994 uint64_t bitpos_m;
996 uint64_t len_h;
998 uint64_t bitpos_h;
999};
1000
1014};
1015
1017#define RTE_PMD_CNXK_MAX_PROT_FIELDS 9
1018
1025 uint64_t logmult;
1027 uint64_t sizem1;
1029 uint64_t offset;
1031 uint64_t valid;
1032};
1033
1042
1045
1048
1053
1059 uint32_t sa_size;
1060
1065 uint32_t max_sa;
1066};
1067
1091__rte_experimental
1093 const struct rte_pmd_cnxk_profile_cfg_params *cfg, uint16_t *profile_id);
1094
1109__rte_experimental
1111 uint16_t profile_id);
1112
1119__rte_experimental
1121#endif /* _PMD_CNXK_H_ */
#define offsetof(TYPE, MEMBER)
Definition: rte_common.h:1066
__rte_experimental union rte_pmd_cnxk_cpt_res_s * rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf)
__rte_experimental const char * rte_pmd_cnxk_model_str_get(void)
rte_pmd_cnxk_sec_action_alg
Definition: rte_pmd_cnxk.h:22
@ RTE_PMD_CNXK_SEC_ACTION_ALG4
Definition: rte_pmd_cnxk.h:47
@ RTE_PMD_CNXK_SEC_ACTION_ALG2
Definition: rte_pmd_cnxk.h:36
@ RTE_PMD_CNXK_SEC_ACTION_ALG1
Definition: rte_pmd_cnxk.h:31
@ RTE_PMD_CNXK_SEC_ACTION_ALG0
Definition: rte_pmd_cnxk.h:26
@ RTE_PMD_CNXK_SEC_ACTION_ALG3
Definition: rte_pmd_cnxk.h:41
rte_pmd_cnxk_cpt_q_stats_type
Definition: rte_pmd_cnxk.h:51
@ RTE_PMD_CNXK_CPT_Q_STATS_ETHDEV
Definition: rte_pmd_cnxk.h:59
@ RTE_PMD_CNXK_CPT_Q_STATS_INL_DEV
Definition: rte_pmd_cnxk.h:53
@ RTE_PMD_CNXK_CPT_Q_STATS_KERNEL
Definition: rte_pmd_cnxk.h:57
struct __rte_aligned(32) rte_pmd_cnxk_ipsec_inb_ctx_msns_reg
Definition: rte_pmd_cnxk.h:366
#define RTE_PMD_CNXK_AR_WINBITS_SZ
Definition: rte_pmd_cnxk.h:106
#define RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_SZ
Definition: rte_pmd_cnxk.h:383
__rte_experimental int rte_pmd_cnxk_cpt_q_stats_get(uint16_t portid, enum rte_pmd_cnxk_cpt_q_stats_type type, struct rte_pmd_cnxk_cpt_q_stats *stats, uint16_t idx)
__rte_experimental int rte_pmd_cnxk_nix_inl_custom_profile_release(uint16_t portid, uint16_t profile_id)
__rte_experimental struct rte_pmd_cnxk_inl_dev_q * rte_pmd_cnxk_inl_dev_qptr_get(void)
__rte_experimental int rte_pmd_cnxk_sa_flush(uint16_t portid, union rte_pmd_cnxk_ipsec_hw_sa *sess, bool inb)
#define RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_OFF
Definition: rte_pmd_cnxk.h:386
__rte_experimental int rte_pmd_cnxk_nix_inl_custom_profile_setup(uint16_t portid, const struct rte_pmd_cnxk_profile_cfg_params *cfg, uint16_t *profile_id)
__rte_experimental union rte_pmd_cnxk_ipsec_hw_sa * rte_pmd_cnxk_inl_inb_prof_sa_base_get(uint16_t portid, uint16_t profile_id)
__rte_experimental void rte_pmd_cnxk_hw_inline_inb_cfg_set(uint16_t portid, struct rte_pmd_cnxk_ipsec_inb_cfg *cfg)
#define RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_U64
Definition: rte_pmd_cnxk.h:350
__rte_experimental union rte_pmd_cnxk_ipsec_hw_sa * rte_pmd_cnxk_hw_session_base_get(uint16_t portid, bool inb)
#define RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_ALIGN_PAD
Definition: rte_pmd_cnxk.h:390
#define RTE_PMD_CNXK_MAX_PROT_FIELDS
#define RTE_PMD_CNXK_IPSEC_INB_MSNS_SPACES
Definition: rte_pmd_cnxk.h:341
rte_pmd_cnxk_nix_rx_prot_e
@ RTE_PMD_CNXK_RX_PROT_PARAM2
@ RTE_PMD_CNXK_RX_PROT_INL_OFFSET
@ RTE_PMD_CNXK_RX_PROT_ALG
@ RTE_PMD_CNXK_RX_PROT_RPTR_H
@ RTE_PMD_CNXK_RX_PROT_SUB_INDEX
@ RTE_PMD_CNXK_RX_PROT_SA_INDEX
@ RTE_PMD_CNXK_RX_PROT_PARAM1
@ RTE_PMD_CNXK_RX_PROT_IP_OFFSET
@ RTE_PMD_CNXK_RX_PROT_OPCODE
__rte_experimental int rte_pmd_cnxk_hw_sa_read(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len, bool inb)
__rte_experimental uint16_t rte_pmd_cnxk_inl_dev_submit(struct rte_pmd_cnxk_inl_dev_q *qptr, void *inst, uint16_t nb_inst)
__rte_experimental int rte_pmd_cnxk_hw_sa_write(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len, bool inb)
uint64_t ar_winbits[RTE_PMD_CNXK_AR_WINBITS_SZ]
Definition: rte_pmd_cnxk.h:139
uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN]
Definition: rte_pmd_cnxk.h:502
union rte_pmd_cnxk_ipsec_inb_msns_sa::@21 w0
union rte_pmd_cnxk_ipsec_inb_msns_sa::@23 w2
union rte_pmd_cnxk_ipsec_inb_msns_sa::@25 w10
struct rte_pmd_cnxk_ipsec_inb_ctx_msns_reg ctx
Definition: rte_pmd_cnxk.h:508
union rte_pmd_cnxk_ipsec_inb_msns_sa::@24 w8
union rte_pmd_cnxk_ipsec_inb_msns_sa::@22 w1
uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN]
Definition: rte_pmd_cnxk.h:476
uint8_t rsvd[RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_SZ - RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_OFF - sizeof(struct rte_pmd_cnxk_ipsec_inb_ctx_msns_reg)]
Definition: rte_pmd_cnxk.h:512
uint8_t ctx_align_pad[RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_ALIGN_PAD]
Definition: rte_pmd_cnxk.h:505
union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr
Definition: rte_pmd_cnxk.h:499
union rte_pmd_cnxk_ipsec_inb_sa::@14 w8
uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN]
Definition: rte_pmd_cnxk.h:334
union rte_pmd_cnxk_ipsec_inb_sa::@15 w10
union rte_pmd_cnxk_ipsec_inb_sa::@12 w1
struct rte_pmd_cnxk_ipsec_inb_ctx_update_reg ctx
Definition: rte_pmd_cnxk.h:337
union rte_pmd_cnxk_ipsec_inb_sa::@13 w2
uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN]
Definition: rte_pmd_cnxk.h:305
union rte_pmd_cnxk_ipsec_inb_sa::@11 w0
union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr
Definition: rte_pmd_cnxk.h:331
union rte_pmd_cnxk_ipsec_outb_sa::@34 w10
struct rte_pmd_cnxk_ipsec_outb_ctx_update_reg ctx
Definition: rte_pmd_cnxk.h:682
uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN]
Definition: rte_pmd_cnxk.h:679
union rte_pmd_cnxk_ipsec_outb_sa::@33 w2
union rte_pmd_cnxk_ipsec_outb_iv iv
Definition: rte_pmd_cnxk.h:653
union rte_pmd_cnxk_ipsec_outb_sa::@32 w1
union rte_pmd_cnxk_ipsec_outb_sa::@31 w0
uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN]
Definition: rte_pmd_cnxk.h:650
union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr
Definition: rte_pmd_cnxk.h:676
uint64_t ipv4_df_src_or_ipv6_flw_lbl_src
Definition: rte_pmd_cnxk.h:628
struct rte_pmd_cnxk_rx_extract_inl_cfg extract_cfg
struct rte_pmd_cnxk_rx_gen_inl_cfg gen_cfg
struct rte_pmd_cnxk_rx_def_inl_cfg def_cfg
struct rte_pmd_cnxk_rx_prot_field_inl_cfg prot_field_cfg[RTE_PMD_CNXK_MAX_PROT_FIELDS]
struct rte_pmd_cnxk_ipsec_inb_msns_sa inb_msns
Definition: rte_pmd_cnxk.h:692
struct rte_pmd_cnxk_ipsec_outb_sa outb
Definition: rte_pmd_cnxk.h:690
struct rte_pmd_cnxk_ipsec_inb_sa inb
Definition: rte_pmd_cnxk.h:688