DPDK 25.03.0-rc0
rte_pmd_cnxk.h
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1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(C) 2022 Marvell.
3 */
4
11#ifndef _PMD_CNXK_H_
12#define _PMD_CNXK_H_
13
14#include <rte_compat.h>
15#include <rte_ethdev.h>
16#include <rte_ether.h>
17#include <rte_security.h>
18
48};
49
60};
61
65 uint64_t enc_pkts;
67 uint64_t enc_bytes;
69 uint64_t dec_pkts;
71 uint64_t dec_bytes;
72};
73
74struct rte_pmd_cnxk_sec_action {
76 uint32_t sa_index;
78 bool sa_xor;
80 uint16_t sa_hi, sa_lo;
85};
86
87#define RTE_PMD_CNXK_CTX_MAX_CKEY_LEN 32
88#define RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN 128
89
91#define RTE_PMD_CNXK_AR_WIN_SIZE_MIN 64
92#define RTE_PMD_CNXK_AR_WIN_SIZE_MAX 4096
93#define RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 5
94
96#define RTE_PMD_CNXK_AR_WINBITS_SZ (RTE_ALIGN_CEIL(RTE_PMD_CNXK_AR_WIN_SIZE_MAX, 64) / 64)
97
100 struct {
102 uint32_t dst_addr;
104 uint32_t src_addr;
105 } ipv4;
106 struct {
108 uint8_t src_addr[16];
110 uint8_t dst_addr[16];
111 } ipv6;
112};
113
117 uint64_t ar_base;
121 uint64_t hard_life;
123 uint64_t soft_life;
125 uint64_t mib_octs;
127 uint64_t mib_pkts;
130};
131
134 uint64_t u64[2];
136 uint8_t iv_dbg[16];
137 struct {
139 uint8_t iv_dbg1[4];
141 uint8_t salt[4];
142
143 uint32_t rsvd;
145 uint8_t iv_dbg2[4];
146 } s;
147};
148
151 union {
152 struct {
153 uint64_t reserved_0_2 : 3;
154 uint64_t address : 57;
155 uint64_t mode : 4;
156 } s;
157 uint64_t u64;
158 } err_ctl;
159
160 uint64_t esn_val;
161 uint64_t hard_life;
162 uint64_t soft_life;
163 uint64_t mib_octs;
164 uint64_t mib_pkts;
165};
166
172 union {
173 struct {
175 uint64_t ar_win : 3;
177 uint64_t hard_life_dec : 1;
179 uint64_t soft_life_dec : 1;
180
182 uint64_t count_glb_octets : 1;
184 uint64_t count_glb_pkts : 1;
186 uint64_t count_mib_bytes : 1;
187
189 uint64_t count_mib_pkts : 1;
191 uint64_t hw_ctx_off : 7;
192
194 uint64_t ctx_id : 16;
195
197 uint64_t orig_pkt_fabs : 1;
199 uint64_t orig_pkt_free : 1;
201 uint64_t pkind : 6;
202
203 uint64_t rsvd0 : 1;
205 uint64_t et_ovrwr : 1;
207 uint64_t pkt_output : 2;
209 uint64_t pkt_format : 1;
211 uint64_t defrag_opt : 2;
213 uint64_t x2p_dst : 1;
214
216 uint64_t ctx_push_size : 7;
217 uint64_t rsvd1 : 1;
218
220 uint64_t ctx_hdr_size : 2;
222 uint64_t aop_valid : 1;
223 uint64_t rsvd2 : 1;
225 uint64_t ctx_size : 4;
226 } s;
227 uint64_t u64;
228 } w0;
229
231 union {
232 struct {
234 uint64_t orig_pkt_aura : 20;
235 uint64_t rsvd3 : 4;
237 uint64_t orig_pkt_foff : 8;
239 uint64_t cookie : 32;
240 } s;
241 uint64_t u64;
242 } w1;
243
245 union {
246 struct {
248 uint64_t valid : 1;
250 uint64_t dir : 1;
251 uint64_t rsvd11 : 1;
252 uint64_t rsvd4 : 1;
254 uint64_t ipsec_mode : 1;
256 uint64_t ipsec_protocol : 1;
258 uint64_t aes_key_len : 2;
259
261 uint64_t enc_type : 3;
263 uint64_t life_unit : 1;
265 uint64_t auth_type : 4;
266
268 uint64_t encap_type : 2;
270 uint64_t et_ovrwr_ddr_en : 1;
272 uint64_t esn_en : 1;
274 uint64_t tport_l4_incr_csum : 1;
276 uint64_t ip_hdr_verify : 2;
278 uint64_t udp_ports_verify : 1;
279
281 uint64_t l3hdr_on_err : 1;
282 uint64_t rsvd6 : 6;
283 uint64_t rsvd12 : 1;
284
286 uint64_t spi : 32;
287 } s;
288 uint64_t u64;
289 } w2;
290
292 uint64_t rsvd7;
293
295 uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN];
296
298 union {
299 struct {
300 uint32_t rsvd8;
302 uint8_t salt[4];
303 } s;
304 uint64_t u64;
305 } w8;
306 uint64_t rsvd9;
307
309 union {
310 struct {
311 uint64_t rsvd10 : 32;
313 uint64_t udp_src_port : 16;
315 uint64_t udp_dst_port : 16;
316 } s;
317 uint64_t u64;
319
322
324 uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN];
325
328};
329
335 union {
336 struct {
338 uint64_t esn_en : 1;
340 uint64_t ip_id : 1;
341 uint64_t rsvd0 : 1;
343 uint64_t hard_life_dec : 1;
345 uint64_t soft_life_dec : 1;
346
348 uint64_t count_glb_octets : 1;
350 uint64_t count_glb_pkts : 1;
352 uint64_t count_mib_bytes : 1;
353
355 uint64_t count_mib_pkts : 1;
357 uint64_t hw_ctx_off : 7;
358
360 uint64_t ctx_id : 16;
361 uint64_t rsvd1 : 16;
362
364 uint64_t ctx_push_size : 7;
365 uint64_t rsvd2 : 1;
366
368 uint64_t ctx_hdr_size : 2;
370 uint64_t aop_valid : 1;
371 uint64_t rsvd3 : 1;
373 uint64_t ctx_size : 4;
374 } s;
375 uint64_t u64;
376 } w0;
377
379 union {
380 struct {
381 uint64_t rsvd4 : 32;
383 uint64_t cookie : 32;
384 } s;
385 uint64_t u64;
386 } w1;
387
389 union {
390 struct {
392 uint64_t valid : 1;
394 uint64_t dir : 1;
395 uint64_t rsvd11 : 1;
396 uint64_t rsvd5 : 1;
398 uint64_t ipsec_mode : 1;
400 uint64_t ipsec_protocol : 1;
401
403 uint64_t aes_key_len : 2;
404
406 uint64_t enc_type : 3;
408 uint64_t life_unit : 1;
410 uint64_t auth_type : 4;
411
413 uint64_t encap_type : 2;
417 uint64_t dscp_src : 1;
419 uint64_t iv_src : 2;
421 uint64_t ipid_gen : 1;
422 uint64_t rsvd6 : 1;
423
424 uint64_t rsvd7 : 7;
425 uint64_t rsvd12 : 1;
426
428 uint64_t spi : 32;
429 } s;
430 uint64_t u64;
431 } w2;
432
434 uint64_t rsvd8;
435
437 uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN];
438
441
443 union {
444 struct {
445 uint64_t rsvd9 : 4;
448
450 uint64_t dscp : 6;
451 uint64_t rsvd10 : 2;
452
454 uint64_t udp_dst_port : 16;
455
457 uint64_t udp_src_port : 16;
458 } s;
459 uint64_t u64;
461
464
466 uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN];
467
470};
471
478};
479
485 uint64_t compcode : 7;
487 uint64_t doneint : 1;
489 uint64_t uc_compcode : 8;
491 uint64_t rlen : 16;
493 uint64_t spi : 32;
494
496 uint64_t esn;
497 } cn10k;
498
502 uint64_t compcode : 8;
504 uint64_t uc_compcode : 8;
506 uint64_t doneint : 1;
507 uint64_t reserved_17_63 : 47;
508
509 uint64_t reserved_64_127;
510 } cn9k;
511
513 uint64_t u64[2];
514};
515
521 uint16_t param1;
525 uint16_t param2;
526};
527
533struct rte_pmd_cnxk_inl_dev_q;
534
552__rte_experimental
553int rte_pmd_cnxk_hw_sa_read(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data,
554 uint32_t len, bool inb);
572__rte_experimental
573int rte_pmd_cnxk_hw_sa_write(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data,
574 uint32_t len, bool inb);
575
590__rte_experimental
592
606__rte_experimental
608
622__rte_experimental
623int rte_pmd_cnxk_sa_flush(uint16_t portid, union rte_pmd_cnxk_ipsec_hw_sa *sess, bool inb);
624
632__rte_experimental
633struct rte_pmd_cnxk_inl_dev_q *rte_pmd_cnxk_inl_dev_qptr_get(void);
634
648__rte_experimental
649uint16_t rte_pmd_cnxk_inl_dev_submit(struct rte_pmd_cnxk_inl_dev_q *qptr, void *inst,
650 uint16_t nb_inst);
651
668__rte_experimental
670 struct rte_pmd_cnxk_cpt_q_stats *stats, uint16_t idx);
671
681__rte_experimental
683
690__rte_experimental
692#endif /* _PMD_CNXK_H_ */
__rte_experimental union rte_pmd_cnxk_cpt_res_s * rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf)
__rte_experimental const char * rte_pmd_cnxk_model_str_get(void)
rte_pmd_cnxk_sec_action_alg
Definition: rte_pmd_cnxk.h:22
@ RTE_PMD_CNXK_SEC_ACTION_ALG4
Definition: rte_pmd_cnxk.h:47
@ RTE_PMD_CNXK_SEC_ACTION_ALG2
Definition: rte_pmd_cnxk.h:36
@ RTE_PMD_CNXK_SEC_ACTION_ALG1
Definition: rte_pmd_cnxk.h:31
@ RTE_PMD_CNXK_SEC_ACTION_ALG0
Definition: rte_pmd_cnxk.h:26
@ RTE_PMD_CNXK_SEC_ACTION_ALG3
Definition: rte_pmd_cnxk.h:41
rte_pmd_cnxk_cpt_q_stats_type
Definition: rte_pmd_cnxk.h:51
@ RTE_PMD_CNXK_CPT_Q_STATS_ETHDEV
Definition: rte_pmd_cnxk.h:59
@ RTE_PMD_CNXK_CPT_Q_STATS_INL_DEV
Definition: rte_pmd_cnxk.h:53
@ RTE_PMD_CNXK_CPT_Q_STATS_KERNEL
Definition: rte_pmd_cnxk.h:57
#define RTE_PMD_CNXK_AR_WINBITS_SZ
Definition: rte_pmd_cnxk.h:96
__rte_experimental int rte_pmd_cnxk_cpt_q_stats_get(uint16_t portid, enum rte_pmd_cnxk_cpt_q_stats_type type, struct rte_pmd_cnxk_cpt_q_stats *stats, uint16_t idx)
__rte_experimental struct rte_pmd_cnxk_inl_dev_q * rte_pmd_cnxk_inl_dev_qptr_get(void)
__rte_experimental int rte_pmd_cnxk_sa_flush(uint16_t portid, union rte_pmd_cnxk_ipsec_hw_sa *sess, bool inb)
__rte_experimental void rte_pmd_cnxk_hw_inline_inb_cfg_set(uint16_t portid, struct rte_pmd_cnxk_ipsec_inb_cfg *cfg)
__rte_experimental union rte_pmd_cnxk_ipsec_hw_sa * rte_pmd_cnxk_hw_session_base_get(uint16_t portid, bool inb)
__rte_experimental int rte_pmd_cnxk_hw_sa_read(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len, bool inb)
__rte_experimental uint16_t rte_pmd_cnxk_inl_dev_submit(struct rte_pmd_cnxk_inl_dev_q *qptr, void *inst, uint16_t nb_inst)
__rte_experimental int rte_pmd_cnxk_hw_sa_write(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len, bool inb)
uint64_t ar_winbits[RTE_PMD_CNXK_AR_WINBITS_SZ]
Definition: rte_pmd_cnxk.h:129
union rte_pmd_cnxk_ipsec_inb_sa::@10 w8
uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN]
Definition: rte_pmd_cnxk.h:324
struct rte_pmd_cnxk_ipsec_inb_ctx_update_reg ctx
Definition: rte_pmd_cnxk.h:327
union rte_pmd_cnxk_ipsec_inb_sa::@11 w10
union rte_pmd_cnxk_ipsec_inb_sa::@7 w0
union rte_pmd_cnxk_ipsec_inb_sa::@9 w2
union rte_pmd_cnxk_ipsec_inb_sa::@8 w1
uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN]
Definition: rte_pmd_cnxk.h:295
union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr
Definition: rte_pmd_cnxk.h:321
union rte_pmd_cnxk_ipsec_outb_sa::@19 w2
struct rte_pmd_cnxk_ipsec_outb_ctx_update_reg ctx
Definition: rte_pmd_cnxk.h:469
uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN]
Definition: rte_pmd_cnxk.h:466
union rte_pmd_cnxk_ipsec_outb_iv iv
Definition: rte_pmd_cnxk.h:440
union rte_pmd_cnxk_ipsec_outb_sa::@17 w0
union rte_pmd_cnxk_ipsec_outb_sa::@18 w1
union rte_pmd_cnxk_ipsec_outb_sa::@20 w10
uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN]
Definition: rte_pmd_cnxk.h:437
union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr
Definition: rte_pmd_cnxk.h:463
uint64_t ipv4_df_src_or_ipv6_flw_lbl_src
Definition: rte_pmd_cnxk.h:415
struct rte_pmd_cnxk_ipsec_outb_sa outb
Definition: rte_pmd_cnxk.h:477
struct rte_pmd_cnxk_ipsec_inb_sa inb
Definition: rte_pmd_cnxk.h:475