14#include <rte_compat.h>
74struct rte_pmd_cnxk_sec_action {
80 uint16_t sa_hi, sa_lo;
94 bool use_custom_profile;
97#define RTE_PMD_CNXK_CTX_MAX_CKEY_LEN 32
98#define RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN 128
101#define RTE_PMD_CNXK_AR_WIN_SIZE_MIN 64
102#define RTE_PMD_CNXK_AR_WIN_SIZE_MAX 4096
103#define RTE_PMD_CNXK_LOG_MIN_AR_WIN_SIZE_M1 5
106#define RTE_PMD_CNXK_AR_WINBITS_SZ (RTE_ALIGN_CEIL(RTE_PMD_CNXK_AR_WIN_SIZE_MAX, 64) / 64)
163 uint64_t reserved_0_2 : 3;
164 uint64_t address : 57;
321 uint64_t rsvd10 : 32;
341#define RTE_PMD_CNXK_IPSEC_INB_MSNS_SPACES 4
344#define RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_BITS 1024
347#define RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_BYTES (RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_BITS / 8)
350#define RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_U64 \
351 (RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_BYTES / sizeof(uint64_t))
366struct __rte_aligned(32) rte_pmd_cnxk_ipsec_inb_ctx_msns_reg {
383#define RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_SZ 1024
386#define RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_OFF \
387 RTE_ALIGN_CEIL(offsetof(struct rte_pmd_cnxk_ipsec_inb_sa, ctx), 32)
390#define RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_ALIGN_PAD \
391 (RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_OFF - offsetof(struct rte_pmd_cnxk_ipsec_inb_sa, ctx))
394#define RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_PUSH_SZ(hw_ctx_off_words) (hw_ctx_off_words)
407 uint64_t hard_life_dec : 1;
408 uint64_t soft_life_dec : 1;
409 uint64_t count_glb_octets : 1;
410 uint64_t count_glb_pkts : 1;
411 uint64_t count_mib_bytes : 1;
412 uint64_t count_mib_pkts : 1;
413 uint64_t hw_ctx_off : 7;
414 uint64_t ctx_id : 16;
415 uint64_t orig_pkt_fabs : 1;
416 uint64_t orig_pkt_free : 1;
419 uint64_t et_ovrwr : 1;
420 uint64_t pkt_output : 2;
421 uint64_t pkt_format : 1;
422 uint64_t defrag_opt : 2;
423 uint64_t x2p_dst : 1;
424 uint64_t ctx_push_size : 7;
426 uint64_t ctx_hdr_size : 2;
427 uint64_t aop_valid : 1;
429 uint64_t ctx_size : 4;
437 uint64_t orig_pkt_aura : 20;
439 uint64_t orig_pkt_foff : 8;
440 uint64_t cookie : 32;
452 uint64_t ipsec_mode : 1;
453 uint64_t ipsec_protocol : 1;
454 uint64_t aes_key_len : 2;
455 uint64_t enc_type : 3;
456 uint64_t life_unit : 1;
457 uint64_t auth_type : 4;
458 uint64_t encap_type : 2;
459 uint64_t et_ovrwr_ddr_en : 1;
461 uint64_t tport_l4_incr_csum : 1;
462 uint64_t ip_hdr_verify : 2;
463 uint64_t udp_ports_verify : 1;
464 uint64_t l3hdr_on_err : 1;
491 uint64_t rsvd10 : 32;
492 uint64_t udp_src_port : 16;
493 uint64_t udp_dst_port : 16;
508 struct rte_pmd_cnxk_ipsec_inb_ctx_msns_reg
ctx;
512 sizeof(
struct rte_pmd_cnxk_ipsec_inb_ctx_msns_reg)];
516 "rte_pmd_cnxk_ipsec_inb_msns_sa must be 1KB");
519 "msns_sa ctx must be 32-byte aligned");
522 "msns_sa ctx must start at Word32");
524 "msns_sa hw_ctx_off must be <= 32 without CTX caching");
526 "msns_sa ar_winbits must be 32-byte aligned");
529 "msns_sa w1 offset must match inb_sa");
532 "msns_sa w2 offset must match inb_sa");
538#define RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_SZ_ALIGN RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_SZ
541#define RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_WR_SZ offsetof(struct rte_pmd_cnxk_ipsec_inb_msns_sa, rsvd)
739 uint64_t reserved_17_63 : 47;
741 uint64_t reserved_64_127;
765struct rte_pmd_cnxk_inl_dev_q;
786 uint32_t len,
bool inb);
806 uint32_t len,
bool inb);
854 uint16_t profile_id);
1017#define RTE_PMD_CNXK_MAX_PROT_FIELDS 9
1111 uint16_t profile_id);
#define offsetof(TYPE, MEMBER)
__rte_experimental union rte_pmd_cnxk_cpt_res_s * rte_pmd_cnxk_inl_ipsec_res(struct rte_mbuf *mbuf)
__rte_experimental const char * rte_pmd_cnxk_model_str_get(void)
rte_pmd_cnxk_sec_action_alg
@ RTE_PMD_CNXK_SEC_ACTION_ALG4
@ RTE_PMD_CNXK_SEC_ACTION_ALG2
@ RTE_PMD_CNXK_SEC_ACTION_ALG1
@ RTE_PMD_CNXK_SEC_ACTION_ALG0
@ RTE_PMD_CNXK_SEC_ACTION_ALG3
rte_pmd_cnxk_cpt_q_stats_type
@ RTE_PMD_CNXK_CPT_Q_STATS_ETHDEV
@ RTE_PMD_CNXK_CPT_Q_STATS_INL_DEV
@ RTE_PMD_CNXK_CPT_Q_STATS_KERNEL
struct __rte_aligned(32) rte_pmd_cnxk_ipsec_inb_ctx_msns_reg
#define RTE_PMD_CNXK_AR_WINBITS_SZ
#define RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_SZ
__rte_experimental int rte_pmd_cnxk_cpt_q_stats_get(uint16_t portid, enum rte_pmd_cnxk_cpt_q_stats_type type, struct rte_pmd_cnxk_cpt_q_stats *stats, uint16_t idx)
__rte_experimental int rte_pmd_cnxk_nix_inl_custom_profile_release(uint16_t portid, uint16_t profile_id)
__rte_experimental struct rte_pmd_cnxk_inl_dev_q * rte_pmd_cnxk_inl_dev_qptr_get(void)
__rte_experimental int rte_pmd_cnxk_sa_flush(uint16_t portid, union rte_pmd_cnxk_ipsec_hw_sa *sess, bool inb)
#define RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_OFF
__rte_experimental int rte_pmd_cnxk_nix_inl_custom_profile_setup(uint16_t portid, const struct rte_pmd_cnxk_profile_cfg_params *cfg, uint16_t *profile_id)
__rte_experimental union rte_pmd_cnxk_ipsec_hw_sa * rte_pmd_cnxk_inl_inb_prof_sa_base_get(uint16_t portid, uint16_t profile_id)
__rte_experimental void rte_pmd_cnxk_hw_inline_inb_cfg_set(uint16_t portid, struct rte_pmd_cnxk_ipsec_inb_cfg *cfg)
#define RTE_PMD_CNXK_IPSEC_INB_MSNS_AR_WIN_U64
__rte_experimental union rte_pmd_cnxk_ipsec_hw_sa * rte_pmd_cnxk_hw_session_base_get(uint16_t portid, bool inb)
#define RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_ALIGN_PAD
#define RTE_PMD_CNXK_MAX_PROT_FIELDS
#define RTE_PMD_CNXK_IPSEC_INB_MSNS_SPACES
rte_pmd_cnxk_nix_rx_prot_e
@ RTE_PMD_CNXK_RX_PROT_PARAM2
@ RTE_PMD_CNXK_RX_PROT_INL_OFFSET
@ RTE_PMD_CNXK_RX_PROT_ALG
@ RTE_PMD_CNXK_RX_PROT_RPTR_H
@ RTE_PMD_CNXK_RX_PROT_SUB_INDEX
@ RTE_PMD_CNXK_RX_PROT_SA_INDEX
@ RTE_PMD_CNXK_RX_PROT_PARAM1
@ RTE_PMD_CNXK_RX_PROT_IP_OFFSET
@ RTE_PMD_CNXK_RX_PROT_OPCODE
__rte_experimental int rte_pmd_cnxk_hw_sa_read(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len, bool inb)
__rte_experimental uint16_t rte_pmd_cnxk_inl_dev_submit(struct rte_pmd_cnxk_inl_dev_q *qptr, void *inst, uint16_t nb_inst)
__rte_experimental int rte_pmd_cnxk_hw_sa_write(uint16_t portid, void *sess, union rte_pmd_cnxk_ipsec_hw_sa *data, uint32_t len, bool inb)
uint64_t ar_winbits[RTE_PMD_CNXK_AR_WINBITS_SZ]
uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN]
union rte_pmd_cnxk_ipsec_inb_msns_sa::@21 w0
union rte_pmd_cnxk_ipsec_inb_msns_sa::@23 w2
union rte_pmd_cnxk_ipsec_inb_msns_sa::@25 w10
struct rte_pmd_cnxk_ipsec_inb_ctx_msns_reg ctx
union rte_pmd_cnxk_ipsec_inb_msns_sa::@24 w8
union rte_pmd_cnxk_ipsec_inb_msns_sa::@22 w1
uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN]
uint8_t rsvd[RTE_PMD_CNXK_IPSEC_INB_SA_MSNS_SZ - RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_OFF - sizeof(struct rte_pmd_cnxk_ipsec_inb_ctx_msns_reg)]
uint8_t ctx_align_pad[RTE_PMD_CNXK_IPSEC_INB_MSNS_CTX_ALIGN_PAD]
union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr
union rte_pmd_cnxk_ipsec_inb_sa::@14 w8
uint64_t count_glb_octets
uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN]
uint64_t tport_l4_incr_csum
union rte_pmd_cnxk_ipsec_inb_sa::@15 w10
union rte_pmd_cnxk_ipsec_inb_sa::@12 w1
struct rte_pmd_cnxk_ipsec_inb_ctx_update_reg ctx
uint64_t udp_ports_verify
union rte_pmd_cnxk_ipsec_inb_sa::@13 w2
uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN]
union rte_pmd_cnxk_ipsec_inb_sa::@11 w0
union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr
union rte_pmd_cnxk_ipsec_outb_sa::@34 w10
struct rte_pmd_cnxk_ipsec_outb_ctx_update_reg ctx
uint64_t count_glb_octets
uint8_t hmac_opad_ipad[RTE_PMD_CNXK_CTX_MAX_OPAD_IPAD_LEN]
union rte_pmd_cnxk_ipsec_outb_sa::@33 w2
union rte_pmd_cnxk_ipsec_outb_iv iv
uint64_t ipv4_df_or_ipv6_flw_lbl
union rte_pmd_cnxk_ipsec_outb_sa::@32 w1
union rte_pmd_cnxk_ipsec_outb_sa::@31 w0
uint8_t cipher_key[RTE_PMD_CNXK_CTX_MAX_CKEY_LEN]
union rte_pmd_cnxk_ipsec_outer_ip_hdr outer_hdr
uint64_t ipv4_df_src_or_ipv6_flw_lbl_src
struct rte_pmd_cnxk_rx_extract_inl_cfg extract_cfg
struct rte_pmd_cnxk_rx_gen_inl_cfg gen_cfg
struct rte_pmd_cnxk_rx_def_inl_cfg def_cfg
struct rte_pmd_cnxk_rx_prot_field_inl_cfg prot_field_cfg[RTE_PMD_CNXK_MAX_PROT_FIELDS]
struct rte_pmd_cnxk_ipsec_inb_msns_sa inb_msns
struct rte_pmd_cnxk_ipsec_outb_sa outb
struct rte_pmd_cnxk_ipsec_inb_sa inb