5 #ifndef _RTE_ETH_CTRL_H_ 6 #define _RTE_ETH_CTRL_H_ 30 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001 31 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002 32 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004 33 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008 34 #define RTE_NTUPLE_FLAGS_PROTO 0x0010 35 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020 37 #define RTE_5TUPLE_FLAGS ( \ 38 RTE_NTUPLE_FLAGS_DST_IP | \ 39 RTE_NTUPLE_FLAGS_SRC_IP | \ 40 RTE_NTUPLE_FLAGS_DST_PORT | \ 41 RTE_NTUPLE_FLAGS_SRC_PORT | \ 42 RTE_NTUPLE_FLAGS_PROTO) 44 #define RTE_2TUPLE_FLAGS ( \ 45 RTE_NTUPLE_FLAGS_DST_PORT | \ 46 RTE_NTUPLE_FLAGS_PROTO) 48 #define RTE_NTUPLE_TCP_FLAGS_MASK 0x3F 54 struct rte_eth_ntuple_filter { 75 #define RTE_ETH_FDIR_MAX_FLEXLEN 16 76 #define RTE_ETH_INSET_SIZE_MAX 128 81 enum rte_eth_input_set_field { 82 RTE_ETH_INPUT_SET_UNKNOWN = 0,
85 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
86 RTE_ETH_INPUT_SET_L2_DST_MAC,
87 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
88 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
89 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
92 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
93 RTE_ETH_INPUT_SET_L3_DST_IP4,
94 RTE_ETH_INPUT_SET_L3_SRC_IP6,
95 RTE_ETH_INPUT_SET_L3_DST_IP6,
96 RTE_ETH_INPUT_SET_L3_IP4_TOS,
97 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
98 RTE_ETH_INPUT_SET_L3_IP6_TC,
99 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
100 RTE_ETH_INPUT_SET_L3_IP4_TTL,
101 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
104 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
105 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
106 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
107 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
108 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
109 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
110 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
113 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
114 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
115 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
116 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
117 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
120 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
121 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
122 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
123 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
124 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
125 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
126 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
127 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
129 RTE_ETH_INPUT_SET_DEFAULT = 65533,
130 RTE_ETH_INPUT_SET_NONE = 65534,
131 RTE_ETH_INPUT_SET_MAX = 65535,
138 RTE_ETH_INPUT_SET_OP_UNKNOWN,
141 RTE_ETH_INPUT_SET_OP_MAX
245 struct rte_ether_addr mac_addr;
252 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
253 RTE_FDIR_TUNNEL_TYPE_NVGRE,
254 RTE_FDIR_TUNNEL_TYPE_VXLAN,
265 struct rte_ether_addr mac_addr;
312 RTE_ETH_FDIR_ACCEPT = 0,
314 RTE_ETH_FDIR_PASSTHRU,
378 RTE_ETH_PAYLOAD_UNKNOWN = 0,
383 RTE_ETH_PAYLOAD_MAX = 8,
433 #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t)) 434 #define RTE_FLOW_MASK_ARRAY_SIZE \ 435 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT) 452 uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
#define RTE_ETH_FDIR_MAX_FLEXLEN
uint32_t flex_payload_unit
uint32_t max_flex_payload_segment_num
uint32_t max_flex_bitmask_num
uint32_t flex_bitmask_unit
uint16_t flex_payload_limit
#define RTE_ETH_INSET_SIZE_MAX
uint8_t mac_addr_byte_mask