28 #define RTE_PDCP_CTRL_PDU_SIZE_MAX 9000u 35 #define RTE_PDCP_MAC_I_LEN 4 42 RTE_PDCP_CTRL_PDU_TYPE_STATUS_REPORT = 0,
43 RTE_PDCP_CTRL_PDU_TYPE_ROHC_FEEDBACK = 1,
44 RTE_PDCP_CTRL_PDU_TYPE_EHC_FEEDBACK = 2,
45 RTE_PDCP_CRTL_PDU_TYPE_UDC_FEEDBACK = 3,
55 RTE_PDCP_PDU_TYPE_CTRL = 0,
56 RTE_PDCP_PDU_TYPE_DATA = 1,
64 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 67 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 79 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 83 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 96 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 100 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 103 uint8_t sn_17_16 : 2;
114 #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN 118 #elif RTE_BYTE_ORDER == RTE_BIG_ENDIAN 120 uint8_t pdu_type : 3;