rte_ethdev.h

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/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2010-2017 Intel Corporation
 */

#ifndef _RTE_ETHDEV_H_
#define _RTE_ETHDEV_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <stdint.h>

/* Use this macro to check if LRO API is supported */
#define RTE_ETHDEV_HAS_LRO_SUPPORT

/* Alias RTE_LIBRTE_ETHDEV_DEBUG for backward compatibility. */
#ifdef RTE_LIBRTE_ETHDEV_DEBUG
#define RTE_ETHDEV_DEBUG_RX
#define RTE_ETHDEV_DEBUG_TX
#endif

#include <rte_cman.h>
#include <rte_compat.h>
#include <rte_log.h>
#include <rte_interrupts.h>
#include <rte_dev.h>
#include <rte_devargs.h>
#include <rte_bitops.h>
#include <rte_errno.h>
#include <rte_common.h>
#include <rte_config.h>
#include <rte_power_intrinsics.h>

#include "rte_ethdev_trace_fp.h"
#include "rte_dev_info.h"

extern int rte_eth_dev_logtype;

#define RTE_ETHDEV_LOG(level, ...) \
    rte_log(RTE_LOG_ ## level, rte_eth_dev_logtype, "" __VA_ARGS__)

struct rte_mbuf;

int rte_eth_iterator_init(struct rte_dev_iterator *iter, const char *devargs);

uint16_t rte_eth_iterator_next(struct rte_dev_iterator *iter);

void rte_eth_iterator_cleanup(struct rte_dev_iterator *iter);

#define RTE_ETH_FOREACH_MATCHING_DEV(id, devargs, iter) \
    for (rte_eth_iterator_init(iter, devargs), \
         id = rte_eth_iterator_next(iter); \
         id != RTE_MAX_ETHPORTS; \
         id = rte_eth_iterator_next(iter))

struct rte_eth_stats {
    uint64_t ipackets;  
    uint64_t opackets;  
    uint64_t ibytes;    
    uint64_t obytes;    
    uint64_t imissed;
    uint64_t ierrors;   
    uint64_t oerrors;   
    uint64_t rx_nombuf; 
    /* Queue stats are limited to max 256 queues */
    uint64_t q_ipackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];
    uint64_t q_opackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];
    uint64_t q_ibytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];
    uint64_t q_obytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];
    uint64_t q_errors[RTE_ETHDEV_QUEUE_STAT_CNTRS];
};

#define RTE_ETH_LINK_SPEED_AUTONEG 0             
#define RTE_ETH_LINK_SPEED_FIXED   RTE_BIT32(0)  
#define RTE_ETH_LINK_SPEED_10M_HD  RTE_BIT32(1)  
#define RTE_ETH_LINK_SPEED_10M     RTE_BIT32(2)  
#define RTE_ETH_LINK_SPEED_100M_HD RTE_BIT32(3)  
#define RTE_ETH_LINK_SPEED_100M    RTE_BIT32(4)  
#define RTE_ETH_LINK_SPEED_1G      RTE_BIT32(5)  
#define RTE_ETH_LINK_SPEED_2_5G    RTE_BIT32(6)  
#define RTE_ETH_LINK_SPEED_5G      RTE_BIT32(7)  
#define RTE_ETH_LINK_SPEED_10G     RTE_BIT32(8)  
#define RTE_ETH_LINK_SPEED_20G     RTE_BIT32(9)  
#define RTE_ETH_LINK_SPEED_25G     RTE_BIT32(10) 
#define RTE_ETH_LINK_SPEED_40G     RTE_BIT32(11) 
#define RTE_ETH_LINK_SPEED_50G     RTE_BIT32(12) 
#define RTE_ETH_LINK_SPEED_56G     RTE_BIT32(13) 
#define RTE_ETH_LINK_SPEED_100G    RTE_BIT32(14) 
#define RTE_ETH_LINK_SPEED_200G    RTE_BIT32(15) 
#define RTE_ETH_LINK_SPEED_400G    RTE_BIT32(16) 
#define RTE_ETH_SPEED_NUM_NONE         0 
#define RTE_ETH_SPEED_NUM_10M         10 
#define RTE_ETH_SPEED_NUM_100M       100 
#define RTE_ETH_SPEED_NUM_1G        1000 
#define RTE_ETH_SPEED_NUM_2_5G      2500 
#define RTE_ETH_SPEED_NUM_5G        5000 
#define RTE_ETH_SPEED_NUM_10G      10000 
#define RTE_ETH_SPEED_NUM_20G      20000 
#define RTE_ETH_SPEED_NUM_25G      25000 
#define RTE_ETH_SPEED_NUM_40G      40000 
#define RTE_ETH_SPEED_NUM_50G      50000 
#define RTE_ETH_SPEED_NUM_56G      56000 
#define RTE_ETH_SPEED_NUM_100G    100000 
#define RTE_ETH_SPEED_NUM_200G    200000 
#define RTE_ETH_SPEED_NUM_400G    400000 
#define RTE_ETH_SPEED_NUM_UNKNOWN UINT32_MAX 
__extension__
struct rte_eth_link {
    uint32_t link_speed;        
    uint16_t link_duplex  : 1;  
    uint16_t link_autoneg : 1;  
    uint16_t link_status  : 1;  
} __rte_aligned(8);      
#define RTE_ETH_LINK_HALF_DUPLEX 0 
#define RTE_ETH_LINK_FULL_DUPLEX 1 
#define RTE_ETH_LINK_DOWN        0 
#define RTE_ETH_LINK_UP          1 
#define RTE_ETH_LINK_FIXED       0 
#define RTE_ETH_LINK_AUTONEG     1 
#define RTE_ETH_LINK_MAX_STR_LEN 40 
struct rte_eth_thresh {
    uint8_t pthresh; 
    uint8_t hthresh; 
    uint8_t wthresh; 
};

#define RTE_ETH_MQ_RX_RSS_FLAG  RTE_BIT32(0) 
#define RTE_ETH_MQ_RX_DCB_FLAG  RTE_BIT32(1) 
#define RTE_ETH_MQ_RX_VMDQ_FLAG RTE_BIT32(2) 
enum rte_eth_rx_mq_mode {

    RTE_ETH_MQ_RX_NONE = 0,

    RTE_ETH_MQ_RX_RSS = RTE_ETH_MQ_RX_RSS_FLAG,
    RTE_ETH_MQ_RX_DCB = RTE_ETH_MQ_RX_DCB_FLAG,
    RTE_ETH_MQ_RX_DCB_RSS = RTE_ETH_MQ_RX_RSS_FLAG | RTE_ETH_MQ_RX_DCB_FLAG,

    RTE_ETH_MQ_RX_VMDQ_ONLY = RTE_ETH_MQ_RX_VMDQ_FLAG,
    RTE_ETH_MQ_RX_VMDQ_RSS = RTE_ETH_MQ_RX_RSS_FLAG | RTE_ETH_MQ_RX_VMDQ_FLAG,
    RTE_ETH_MQ_RX_VMDQ_DCB = RTE_ETH_MQ_RX_VMDQ_FLAG | RTE_ETH_MQ_RX_DCB_FLAG,
    RTE_ETH_MQ_RX_VMDQ_DCB_RSS = RTE_ETH_MQ_RX_RSS_FLAG | RTE_ETH_MQ_RX_DCB_FLAG |
                 RTE_ETH_MQ_RX_VMDQ_FLAG,
};

enum rte_eth_tx_mq_mode {
    RTE_ETH_MQ_TX_NONE    = 0,  
    RTE_ETH_MQ_TX_DCB,          
    RTE_ETH_MQ_TX_VMDQ_DCB,     
    RTE_ETH_MQ_TX_VMDQ_ONLY,    
};

struct rte_eth_rxmode {
    enum rte_eth_rx_mq_mode mq_mode;
    uint32_t mtu;  
    uint32_t max_lro_pkt_size;
    uint64_t offloads;

    uint64_t reserved_64s[2]; 
    void *reserved_ptrs[2];   
};

enum rte_vlan_type {
    RTE_ETH_VLAN_TYPE_UNKNOWN = 0,
    RTE_ETH_VLAN_TYPE_INNER, 
    RTE_ETH_VLAN_TYPE_OUTER, 
    RTE_ETH_VLAN_TYPE_MAX,
};

struct rte_vlan_filter_conf {
    uint64_t ids[64];
};

struct rte_eth_rss_conf {
    uint8_t *rss_key;    
    uint8_t rss_key_len; 
    uint64_t rss_hf;     
};

/*
 * A packet can be identified by hardware as different flow types. Different
 * NIC hardware may support different flow types.
 * Basically, the NIC hardware identifies the flow type as deep protocol as
 * possible, and exclusively. For example, if a packet is identified as
 * 'RTE_ETH_FLOW_NONFRAG_IPV4_TCP', it will not be any of other flow types,
 * though it is an actual IPV4 packet.
 */
#define RTE_ETH_FLOW_UNKNOWN             0
#define RTE_ETH_FLOW_RAW                 1
#define RTE_ETH_FLOW_IPV4                2
#define RTE_ETH_FLOW_FRAG_IPV4           3
#define RTE_ETH_FLOW_NONFRAG_IPV4_TCP    4
#define RTE_ETH_FLOW_NONFRAG_IPV4_UDP    5
#define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP   6
#define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER  7
#define RTE_ETH_FLOW_IPV6                8
#define RTE_ETH_FLOW_FRAG_IPV6           9
#define RTE_ETH_FLOW_NONFRAG_IPV6_TCP   10
#define RTE_ETH_FLOW_NONFRAG_IPV6_UDP   11
#define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP  12
#define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13
#define RTE_ETH_FLOW_L2_PAYLOAD         14
#define RTE_ETH_FLOW_IPV6_EX            15
#define RTE_ETH_FLOW_IPV6_TCP_EX        16
#define RTE_ETH_FLOW_IPV6_UDP_EX        17

#define RTE_ETH_FLOW_PORT               18
#define RTE_ETH_FLOW_VXLAN              19 
#define RTE_ETH_FLOW_GENEVE             20 
#define RTE_ETH_FLOW_NVGRE              21 
#define RTE_ETH_FLOW_VXLAN_GPE          22 
#define RTE_ETH_FLOW_GTPU               23 
#define RTE_ETH_FLOW_MAX                24

/*
 * Below macros are defined for RSS offload types, they can be used to
 * fill rte_eth_rss_conf.rss_hf or rte_flow_action_rss.types.
 */
#define RTE_ETH_RSS_IPV4               RTE_BIT64(2)
#define RTE_ETH_RSS_FRAG_IPV4          RTE_BIT64(3)
#define RTE_ETH_RSS_NONFRAG_IPV4_TCP   RTE_BIT64(4)
#define RTE_ETH_RSS_NONFRAG_IPV4_UDP   RTE_BIT64(5)
#define RTE_ETH_RSS_NONFRAG_IPV4_SCTP  RTE_BIT64(6)
#define RTE_ETH_RSS_NONFRAG_IPV4_OTHER RTE_BIT64(7)
#define RTE_ETH_RSS_IPV6               RTE_BIT64(8)
#define RTE_ETH_RSS_FRAG_IPV6          RTE_BIT64(9)
#define RTE_ETH_RSS_NONFRAG_IPV6_TCP   RTE_BIT64(10)
#define RTE_ETH_RSS_NONFRAG_IPV6_UDP   RTE_BIT64(11)
#define RTE_ETH_RSS_NONFRAG_IPV6_SCTP  RTE_BIT64(12)
#define RTE_ETH_RSS_NONFRAG_IPV6_OTHER RTE_BIT64(13)
#define RTE_ETH_RSS_L2_PAYLOAD         RTE_BIT64(14)
#define RTE_ETH_RSS_IPV6_EX            RTE_BIT64(15)
#define RTE_ETH_RSS_IPV6_TCP_EX        RTE_BIT64(16)
#define RTE_ETH_RSS_IPV6_UDP_EX        RTE_BIT64(17)
#define RTE_ETH_RSS_PORT               RTE_BIT64(18)
#define RTE_ETH_RSS_VXLAN              RTE_BIT64(19)
#define RTE_ETH_RSS_GENEVE             RTE_BIT64(20)
#define RTE_ETH_RSS_NVGRE              RTE_BIT64(21)
#define RTE_ETH_RSS_GTPU               RTE_BIT64(23)
#define RTE_ETH_RSS_ETH                RTE_BIT64(24)
#define RTE_ETH_RSS_S_VLAN             RTE_BIT64(25)
#define RTE_ETH_RSS_C_VLAN             RTE_BIT64(26)
#define RTE_ETH_RSS_ESP                RTE_BIT64(27)
#define RTE_ETH_RSS_AH                 RTE_BIT64(28)
#define RTE_ETH_RSS_L2TPV3             RTE_BIT64(29)
#define RTE_ETH_RSS_PFCP               RTE_BIT64(30)
#define RTE_ETH_RSS_PPPOE              RTE_BIT64(31)
#define RTE_ETH_RSS_ECPRI              RTE_BIT64(32)
#define RTE_ETH_RSS_MPLS               RTE_BIT64(33)
#define RTE_ETH_RSS_IPV4_CHKSUM        RTE_BIT64(34)

#define RTE_ETH_RSS_L4_CHKSUM          RTE_BIT64(35)

#define RTE_ETH_RSS_L2TPV2             RTE_BIT64(36)

/*
 * We use the following macros to combine with above RTE_ETH_RSS_* for
 * more specific input set selection. These bits are defined starting
 * from the high end of the 64 bits.
 * Note: If we use above RTE_ETH_RSS_* without SRC/DST_ONLY, it represents
 * both SRC and DST are taken into account. If SRC_ONLY and DST_ONLY of
 * the same level are used simultaneously, it is the same case as none of
 * them are added.
 */
#define RTE_ETH_RSS_L3_SRC_ONLY        RTE_BIT64(63)
#define RTE_ETH_RSS_L3_DST_ONLY        RTE_BIT64(62)
#define RTE_ETH_RSS_L4_SRC_ONLY        RTE_BIT64(61)
#define RTE_ETH_RSS_L4_DST_ONLY        RTE_BIT64(60)
#define RTE_ETH_RSS_L2_SRC_ONLY        RTE_BIT64(59)
#define RTE_ETH_RSS_L2_DST_ONLY        RTE_BIT64(58)

/*
 * Only select IPV6 address prefix as RSS input set according to
 * https://tools.ietf.org/html/rfc6052
 * Must be combined with RTE_ETH_RSS_IPV6, RTE_ETH_RSS_NONFRAG_IPV6_UDP,
 * RTE_ETH_RSS_NONFRAG_IPV6_TCP, RTE_ETH_RSS_NONFRAG_IPV6_SCTP.
 */
#define RTE_ETH_RSS_L3_PRE32           RTE_BIT64(57)
#define RTE_ETH_RSS_L3_PRE40           RTE_BIT64(56)
#define RTE_ETH_RSS_L3_PRE48           RTE_BIT64(55)
#define RTE_ETH_RSS_L3_PRE56           RTE_BIT64(54)
#define RTE_ETH_RSS_L3_PRE64           RTE_BIT64(53)
#define RTE_ETH_RSS_L3_PRE96           RTE_BIT64(52)

/*
 * Use the following macros to combine with the above layers
 * to choose inner and outer layers or both for RSS computation.
 * Bits 50 and 51 are reserved for this.
 */

#define RTE_ETH_RSS_LEVEL_PMD_DEFAULT  (UINT64_C(0) << 50)

#define RTE_ETH_RSS_LEVEL_OUTERMOST    (UINT64_C(1) << 50)

#define RTE_ETH_RSS_LEVEL_INNERMOST    (UINT64_C(2) << 50)
#define RTE_ETH_RSS_LEVEL_MASK         (UINT64_C(3) << 50)

#define RTE_ETH_RSS_LEVEL(rss_hf) ((rss_hf & RTE_ETH_RSS_LEVEL_MASK) >> 50)

static inline uint64_t
rte_eth_rss_hf_refine(uint64_t rss_hf)
{
    if ((rss_hf & RTE_ETH_RSS_L3_SRC_ONLY) && (rss_hf & RTE_ETH_RSS_L3_DST_ONLY))
        rss_hf &= ~(RTE_ETH_RSS_L3_SRC_ONLY | RTE_ETH_RSS_L3_DST_ONLY);

    if ((rss_hf & RTE_ETH_RSS_L4_SRC_ONLY) && (rss_hf & RTE_ETH_RSS_L4_DST_ONLY))
        rss_hf &= ~(RTE_ETH_RSS_L4_SRC_ONLY | RTE_ETH_RSS_L4_DST_ONLY);

    return rss_hf;
}

#define RTE_ETH_RSS_IPV6_PRE32 ( \
        RTE_ETH_RSS_IPV6 | \
        RTE_ETH_RSS_L3_PRE32)

#define RTE_ETH_RSS_IPV6_PRE40 ( \
        RTE_ETH_RSS_IPV6 | \
        RTE_ETH_RSS_L3_PRE40)

#define RTE_ETH_RSS_IPV6_PRE48 ( \
        RTE_ETH_RSS_IPV6 | \
        RTE_ETH_RSS_L3_PRE48)

#define RTE_ETH_RSS_IPV6_PRE56 ( \
        RTE_ETH_RSS_IPV6 | \
        RTE_ETH_RSS_L3_PRE56)

#define RTE_ETH_RSS_IPV6_PRE64 ( \
        RTE_ETH_RSS_IPV6 | \
        RTE_ETH_RSS_L3_PRE64)

#define RTE_ETH_RSS_IPV6_PRE96 ( \
        RTE_ETH_RSS_IPV6 | \
        RTE_ETH_RSS_L3_PRE96)

#define RTE_ETH_RSS_IPV6_PRE32_UDP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
        RTE_ETH_RSS_L3_PRE32)

#define RTE_ETH_RSS_IPV6_PRE40_UDP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
        RTE_ETH_RSS_L3_PRE40)

#define RTE_ETH_RSS_IPV6_PRE48_UDP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
        RTE_ETH_RSS_L3_PRE48)

#define RTE_ETH_RSS_IPV6_PRE56_UDP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
        RTE_ETH_RSS_L3_PRE56)

#define RTE_ETH_RSS_IPV6_PRE64_UDP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
        RTE_ETH_RSS_L3_PRE64)

#define RTE_ETH_RSS_IPV6_PRE96_UDP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
        RTE_ETH_RSS_L3_PRE96)

#define RTE_ETH_RSS_IPV6_PRE32_TCP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
        RTE_ETH_RSS_L3_PRE32)

#define RTE_ETH_RSS_IPV6_PRE40_TCP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
        RTE_ETH_RSS_L3_PRE40)

#define RTE_ETH_RSS_IPV6_PRE48_TCP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
        RTE_ETH_RSS_L3_PRE48)

#define RTE_ETH_RSS_IPV6_PRE56_TCP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
        RTE_ETH_RSS_L3_PRE56)

#define RTE_ETH_RSS_IPV6_PRE64_TCP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
        RTE_ETH_RSS_L3_PRE64)

#define RTE_ETH_RSS_IPV6_PRE96_TCP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
        RTE_ETH_RSS_L3_PRE96)

#define RTE_ETH_RSS_IPV6_PRE32_SCTP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
        RTE_ETH_RSS_L3_PRE32)

#define RTE_ETH_RSS_IPV6_PRE40_SCTP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
        RTE_ETH_RSS_L3_PRE40)

#define RTE_ETH_RSS_IPV6_PRE48_SCTP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
        RTE_ETH_RSS_L3_PRE48)

#define RTE_ETH_RSS_IPV6_PRE56_SCTP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
        RTE_ETH_RSS_L3_PRE56)

#define RTE_ETH_RSS_IPV6_PRE64_SCTP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
        RTE_ETH_RSS_L3_PRE64)

#define RTE_ETH_RSS_IPV6_PRE96_SCTP ( \
        RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
        RTE_ETH_RSS_L3_PRE96)

#define RTE_ETH_RSS_IP ( \
    RTE_ETH_RSS_IPV4 | \
    RTE_ETH_RSS_FRAG_IPV4 | \
    RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \
    RTE_ETH_RSS_IPV6 | \
    RTE_ETH_RSS_FRAG_IPV6 | \
    RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \
    RTE_ETH_RSS_IPV6_EX)

#define RTE_ETH_RSS_UDP ( \
    RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
    RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
    RTE_ETH_RSS_IPV6_UDP_EX)

#define RTE_ETH_RSS_TCP ( \
    RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
    RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
    RTE_ETH_RSS_IPV6_TCP_EX)

#define RTE_ETH_RSS_SCTP ( \
    RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \
    RTE_ETH_RSS_NONFRAG_IPV6_SCTP)

#define RTE_ETH_RSS_TUNNEL ( \
    RTE_ETH_RSS_VXLAN  | \
    RTE_ETH_RSS_GENEVE | \
    RTE_ETH_RSS_NVGRE)

#define RTE_ETH_RSS_VLAN ( \
    RTE_ETH_RSS_S_VLAN  | \
    RTE_ETH_RSS_C_VLAN)

#define RTE_ETH_RSS_PROTO_MASK ( \
    RTE_ETH_RSS_IPV4 | \
    RTE_ETH_RSS_FRAG_IPV4 | \
    RTE_ETH_RSS_NONFRAG_IPV4_TCP | \
    RTE_ETH_RSS_NONFRAG_IPV4_UDP | \
    RTE_ETH_RSS_NONFRAG_IPV4_SCTP | \
    RTE_ETH_RSS_NONFRAG_IPV4_OTHER | \
    RTE_ETH_RSS_IPV6 | \
    RTE_ETH_RSS_FRAG_IPV6 | \
    RTE_ETH_RSS_NONFRAG_IPV6_TCP | \
    RTE_ETH_RSS_NONFRAG_IPV6_UDP | \
    RTE_ETH_RSS_NONFRAG_IPV6_SCTP | \
    RTE_ETH_RSS_NONFRAG_IPV6_OTHER | \
    RTE_ETH_RSS_L2_PAYLOAD | \
    RTE_ETH_RSS_IPV6_EX | \
    RTE_ETH_RSS_IPV6_TCP_EX | \
    RTE_ETH_RSS_IPV6_UDP_EX | \
    RTE_ETH_RSS_PORT  | \
    RTE_ETH_RSS_VXLAN | \
    RTE_ETH_RSS_GENEVE | \
    RTE_ETH_RSS_NVGRE | \
    RTE_ETH_RSS_MPLS)

/*
 * Definitions used for redirection table entry size.
 * Some RSS RETA sizes may not be supported by some drivers, check the
 * documentation or the description of relevant functions for more details.
 */
#define RTE_ETH_RSS_RETA_SIZE_64  64
#define RTE_ETH_RSS_RETA_SIZE_128 128
#define RTE_ETH_RSS_RETA_SIZE_256 256
#define RTE_ETH_RSS_RETA_SIZE_512 512
#define RTE_ETH_RETA_GROUP_SIZE   64

#define RTE_ETH_VMDQ_MAX_VLAN_FILTERS   64 
#define RTE_ETH_DCB_NUM_USER_PRIORITIES 8  
#define RTE_ETH_VMDQ_DCB_NUM_QUEUES     128 
#define RTE_ETH_DCB_NUM_QUEUES          128 
#define RTE_ETH_DCB_PG_SUPPORT      RTE_BIT32(0) 
#define RTE_ETH_DCB_PFC_SUPPORT     RTE_BIT32(1) 
#define RTE_ETH_VLAN_STRIP_OFFLOAD   0x0001 
#define RTE_ETH_VLAN_FILTER_OFFLOAD  0x0002 
#define RTE_ETH_VLAN_EXTEND_OFFLOAD  0x0004 
#define RTE_ETH_QINQ_STRIP_OFFLOAD   0x0008 
#define RTE_ETH_VLAN_STRIP_MASK      0x0001 
#define RTE_ETH_VLAN_FILTER_MASK     0x0002 
#define RTE_ETH_VLAN_EXTEND_MASK     0x0004 
#define RTE_ETH_QINQ_STRIP_MASK      0x0008 
#define RTE_ETH_VLAN_ID_MAX          0x0FFF 
/* Definitions used for receive MAC address   */
#define RTE_ETH_NUM_RECEIVE_MAC_ADDR   128 
/* Definitions used for unicast hash  */
#define RTE_ETH_VMDQ_NUM_UC_HASH_ARRAY 128 
#define RTE_ETH_VMDQ_ACCEPT_UNTAG      RTE_BIT32(0)

#define RTE_ETH_VMDQ_ACCEPT_HASH_MC    RTE_BIT32(1)

#define RTE_ETH_VMDQ_ACCEPT_HASH_UC    RTE_BIT32(2)

#define RTE_ETH_VMDQ_ACCEPT_BROADCAST  RTE_BIT32(3)

#define RTE_ETH_VMDQ_ACCEPT_MULTICAST  RTE_BIT32(4)

struct rte_eth_rss_reta_entry64 {
    uint64_t mask;
    uint16_t reta[RTE_ETH_RETA_GROUP_SIZE];
};

enum rte_eth_nb_tcs {
    RTE_ETH_4_TCS = 4, 
    RTE_ETH_8_TCS = 8  
};

enum rte_eth_nb_pools {
    RTE_ETH_8_POOLS = 8,    
    RTE_ETH_16_POOLS = 16,  
    RTE_ETH_32_POOLS = 32,  
    RTE_ETH_64_POOLS = 64   
};

/* This structure may be extended in future. */
struct rte_eth_dcb_rx_conf {
    enum rte_eth_nb_tcs nb_tcs; 
    uint8_t dcb_tc[RTE_ETH_DCB_NUM_USER_PRIORITIES];
};

struct rte_eth_vmdq_dcb_tx_conf {
    enum rte_eth_nb_pools nb_queue_pools; 
    uint8_t dcb_tc[RTE_ETH_DCB_NUM_USER_PRIORITIES];
};

struct rte_eth_dcb_tx_conf {
    enum rte_eth_nb_tcs nb_tcs; 
    uint8_t dcb_tc[RTE_ETH_DCB_NUM_USER_PRIORITIES];
};

struct rte_eth_vmdq_tx_conf {
    enum rte_eth_nb_pools nb_queue_pools; 
};

struct rte_eth_vmdq_dcb_conf {
    enum rte_eth_nb_pools nb_queue_pools; 
    uint8_t enable_default_pool; 
    uint8_t default_pool; 
    uint8_t nb_pool_maps; 
    struct {
        uint16_t vlan_id; 
        uint64_t pools;   
    } pool_map[RTE_ETH_VMDQ_MAX_VLAN_FILTERS]; 
    uint8_t dcb_tc[RTE_ETH_DCB_NUM_USER_PRIORITIES];
};

struct rte_eth_vmdq_rx_conf {
    enum rte_eth_nb_pools nb_queue_pools; 
    uint8_t enable_default_pool; 
    uint8_t default_pool; 
    uint8_t enable_loop_back; 
    uint8_t nb_pool_maps; 
    uint32_t rx_mode; 
    struct {
        uint16_t vlan_id; 
        uint64_t pools;   
    } pool_map[RTE_ETH_VMDQ_MAX_VLAN_FILTERS]; 
};

struct rte_eth_txmode {
    enum rte_eth_tx_mq_mode mq_mode; 
    uint64_t offloads;

    uint16_t pvid;
    __extension__
    uint8_t 
        hw_vlan_reject_tagged : 1,
        hw_vlan_reject_untagged : 1,
        hw_vlan_insert_pvid : 1;

    uint64_t reserved_64s[2]; 
    void *reserved_ptrs[2];   
};

struct rte_eth_rxseg_split {
    struct rte_mempool *mp; 
    uint16_t length; 
    uint16_t offset; 
    uint32_t proto_hdr;
};

union rte_eth_rxseg {
    /* The settings for buffer split offload. */
    struct rte_eth_rxseg_split split;
    /* The other features settings should be added here. */
};

struct rte_eth_rxconf {
    struct rte_eth_thresh rx_thresh; 
    uint16_t rx_free_thresh; 
    uint8_t rx_drop_en; 
    uint8_t rx_deferred_start; 
    uint16_t rx_nseg; 
    uint16_t share_group;
    uint16_t share_qid; 
    uint64_t offloads;
    union rte_eth_rxseg *rx_seg;

    struct rte_mempool **rx_mempools;
    uint16_t rx_nmempool; 
    uint64_t reserved_64s[2]; 
    void *reserved_ptrs[2];   
};

struct rte_eth_txconf {
    struct rte_eth_thresh tx_thresh; 
    uint16_t tx_rs_thresh; 
    uint16_t tx_free_thresh; 
    uint8_t tx_deferred_start; 
    uint64_t offloads;

    uint64_t reserved_64s[2]; 
    void *reserved_ptrs[2];   
};

struct rte_eth_hairpin_queue_cap {
    uint32_t locked_device_memory:1;

    uint32_t rte_memory:1;

    uint32_t reserved:30; 
};

struct rte_eth_hairpin_cap {
    uint16_t max_nb_queues;
    uint16_t max_rx_2_tx;
    uint16_t max_tx_2_rx;
    uint16_t max_nb_desc; 
    struct rte_eth_hairpin_queue_cap rx_cap; 
    struct rte_eth_hairpin_queue_cap tx_cap; 
};

#define RTE_ETH_MAX_HAIRPIN_PEERS 32

struct rte_eth_hairpin_peer {
    uint16_t port; 
    uint16_t queue; 
};

struct rte_eth_hairpin_conf {
    uint32_t peer_count:16; 
    uint32_t tx_explicit:1;

    uint32_t manual_bind:1;

    uint32_t use_locked_device_memory:1;

    uint32_t use_rte_memory:1;

    uint32_t force_memory:1;

    uint32_t reserved:11; 
    struct rte_eth_hairpin_peer peers[RTE_ETH_MAX_HAIRPIN_PEERS];
};

struct rte_eth_desc_lim {
    uint16_t nb_max;   
    uint16_t nb_min;   
    uint16_t nb_align; 
    uint16_t nb_seg_max;

    uint16_t nb_mtu_seg_max;
};

enum rte_eth_fc_mode {
    RTE_ETH_FC_NONE = 0, 
    RTE_ETH_FC_RX_PAUSE, 
    RTE_ETH_FC_TX_PAUSE, 
    RTE_ETH_FC_FULL      
};

struct rte_eth_fc_conf {
    uint32_t high_water;  
    uint32_t low_water;   
    uint16_t pause_time;  
    uint16_t send_xon;    
    enum rte_eth_fc_mode mode;  
    uint8_t mac_ctrl_frame_fwd; 
    uint8_t autoneg;      
};

struct rte_eth_pfc_conf {
    struct rte_eth_fc_conf fc; 
    uint8_t priority;          
};

struct rte_eth_pfc_queue_info {
    uint8_t tc_max;
    enum rte_eth_fc_mode mode_capa;
};

struct rte_eth_pfc_queue_conf {
    enum rte_eth_fc_mode mode; 
    struct {
        uint16_t tx_qid; 
        uint8_t tc;
    } rx_pause; /* Valid when (mode == FC_RX_PAUSE || mode == FC_FULL) */

    struct {
        uint16_t pause_time; 
        uint16_t rx_qid;     
        uint8_t tc;
    } tx_pause; /* Valid when (mode == FC_TX_PAUSE || mode == FC_FULL) */
};

enum rte_eth_tunnel_type {
    RTE_ETH_TUNNEL_TYPE_NONE = 0,
    RTE_ETH_TUNNEL_TYPE_VXLAN,
    RTE_ETH_TUNNEL_TYPE_GENEVE,
    RTE_ETH_TUNNEL_TYPE_TEREDO,
    RTE_ETH_TUNNEL_TYPE_NVGRE,
    RTE_ETH_TUNNEL_TYPE_IP_IN_GRE,
    RTE_ETH_L2_TUNNEL_TYPE_E_TAG,
    RTE_ETH_TUNNEL_TYPE_VXLAN_GPE,
    RTE_ETH_TUNNEL_TYPE_ECPRI,
    RTE_ETH_TUNNEL_TYPE_MAX,
};

/* Deprecated API file for rte_eth_dev_filter_* functions */
#include "rte_eth_ctrl.h"

struct rte_eth_udp_tunnel {
    uint16_t udp_port; 
    uint8_t prot_type; 
};

struct rte_eth_intr_conf {
    uint32_t lsc:1;
    uint32_t rxq:1;
    uint32_t rmv:1;
};

#define rte_intr_conf rte_eth_intr_conf

struct rte_eth_conf {
    uint32_t link_speeds; 
    struct rte_eth_rxmode rxmode; 
    struct rte_eth_txmode txmode; 
    uint32_t lpbk_mode; 
    struct {
        struct rte_eth_rss_conf rss_conf; 
        struct rte_eth_vmdq_dcb_conf vmdq_dcb_conf;
        struct rte_eth_dcb_rx_conf dcb_rx_conf;
        struct rte_eth_vmdq_rx_conf vmdq_rx_conf;
    } rx_adv_conf; 
    union {
        struct rte_eth_vmdq_dcb_tx_conf vmdq_dcb_tx_conf;
        struct rte_eth_dcb_tx_conf dcb_tx_conf;
        struct rte_eth_vmdq_tx_conf vmdq_tx_conf;
    } tx_adv_conf; 
    uint32_t dcb_capability_en;
    struct rte_eth_intr_conf intr_conf; 
};

#define RTE_ETH_RX_OFFLOAD_VLAN_STRIP       RTE_BIT64(0)
#define RTE_ETH_RX_OFFLOAD_IPV4_CKSUM       RTE_BIT64(1)
#define RTE_ETH_RX_OFFLOAD_UDP_CKSUM        RTE_BIT64(2)
#define RTE_ETH_RX_OFFLOAD_TCP_CKSUM        RTE_BIT64(3)
#define RTE_ETH_RX_OFFLOAD_TCP_LRO          RTE_BIT64(4)
#define RTE_ETH_RX_OFFLOAD_QINQ_STRIP       RTE_BIT64(5)
#define RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM RTE_BIT64(6)
#define RTE_ETH_RX_OFFLOAD_MACSEC_STRIP     RTE_BIT64(7)
#define RTE_ETH_RX_OFFLOAD_VLAN_FILTER      RTE_BIT64(9)
#define RTE_ETH_RX_OFFLOAD_VLAN_EXTEND      RTE_BIT64(10)
#define RTE_ETH_RX_OFFLOAD_SCATTER          RTE_BIT64(13)

#define RTE_ETH_RX_OFFLOAD_TIMESTAMP        RTE_BIT64(14)
#define RTE_ETH_RX_OFFLOAD_SECURITY         RTE_BIT64(15)
#define RTE_ETH_RX_OFFLOAD_KEEP_CRC         RTE_BIT64(16)
#define RTE_ETH_RX_OFFLOAD_SCTP_CKSUM       RTE_BIT64(17)
#define RTE_ETH_RX_OFFLOAD_OUTER_UDP_CKSUM  RTE_BIT64(18)
#define RTE_ETH_RX_OFFLOAD_RSS_HASH         RTE_BIT64(19)
#define RTE_ETH_RX_OFFLOAD_BUFFER_SPLIT     RTE_BIT64(20)

#define RTE_ETH_RX_OFFLOAD_CHECKSUM (RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | \
                 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | \
                 RTE_ETH_RX_OFFLOAD_TCP_CKSUM)
#define RTE_ETH_RX_OFFLOAD_VLAN (RTE_ETH_RX_OFFLOAD_VLAN_STRIP | \
                 RTE_ETH_RX_OFFLOAD_VLAN_FILTER | \
                 RTE_ETH_RX_OFFLOAD_VLAN_EXTEND | \
                 RTE_ETH_RX_OFFLOAD_QINQ_STRIP)

/*
 * If new Rx offload capabilities are defined, they also must be
 * mentioned in rte_rx_offload_names in rte_ethdev.c file.
 */

#define RTE_ETH_TX_OFFLOAD_VLAN_INSERT      RTE_BIT64(0)
#define RTE_ETH_TX_OFFLOAD_IPV4_CKSUM       RTE_BIT64(1)
#define RTE_ETH_TX_OFFLOAD_UDP_CKSUM        RTE_BIT64(2)
#define RTE_ETH_TX_OFFLOAD_TCP_CKSUM        RTE_BIT64(3)
#define RTE_ETH_TX_OFFLOAD_SCTP_CKSUM       RTE_BIT64(4)
#define RTE_ETH_TX_OFFLOAD_TCP_TSO          RTE_BIT64(5)
#define RTE_ETH_TX_OFFLOAD_UDP_TSO          RTE_BIT64(6)
#define RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM RTE_BIT64(7)  
#define RTE_ETH_TX_OFFLOAD_QINQ_INSERT      RTE_BIT64(8)
#define RTE_ETH_TX_OFFLOAD_VXLAN_TNL_TSO    RTE_BIT64(9)  
#define RTE_ETH_TX_OFFLOAD_GRE_TNL_TSO      RTE_BIT64(10) 
#define RTE_ETH_TX_OFFLOAD_IPIP_TNL_TSO     RTE_BIT64(11) 
#define RTE_ETH_TX_OFFLOAD_GENEVE_TNL_TSO   RTE_BIT64(12) 
#define RTE_ETH_TX_OFFLOAD_MACSEC_INSERT    RTE_BIT64(13)

#define RTE_ETH_TX_OFFLOAD_MT_LOCKFREE      RTE_BIT64(14)

#define RTE_ETH_TX_OFFLOAD_MULTI_SEGS       RTE_BIT64(15)

#define RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE   RTE_BIT64(16)
#define RTE_ETH_TX_OFFLOAD_SECURITY         RTE_BIT64(17)

#define RTE_ETH_TX_OFFLOAD_UDP_TNL_TSO      RTE_BIT64(18)

#define RTE_ETH_TX_OFFLOAD_IP_TNL_TSO       RTE_BIT64(19)

#define RTE_ETH_TX_OFFLOAD_OUTER_UDP_CKSUM  RTE_BIT64(20)

#define RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP RTE_BIT64(21)
/*
 * If new Tx offload capabilities are defined, they also must be
 * mentioned in rte_tx_offload_names in rte_ethdev.c file.
 */

#define RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP RTE_BIT64(0)

#define RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP RTE_BIT64(1)

#define RTE_ETH_DEV_CAPA_RXQ_SHARE              RTE_BIT64(2)

#define RTE_ETH_DEV_CAPA_FLOW_RULE_KEEP         RTE_BIT64(3)

#define RTE_ETH_DEV_CAPA_FLOW_SHARED_OBJECT_KEEP RTE_BIT64(4)

/*
 * Fallback default preferred Rx/Tx port parameters.
 * These are used if an application requests default parameters
 * but the PMD does not provide preferred values.
 */
#define RTE_ETH_DEV_FALLBACK_RX_RINGSIZE 512
#define RTE_ETH_DEV_FALLBACK_TX_RINGSIZE 512
#define RTE_ETH_DEV_FALLBACK_RX_NBQUEUES 1
#define RTE_ETH_DEV_FALLBACK_TX_NBQUEUES 1

struct rte_eth_dev_portconf {
    uint16_t burst_size; 
    uint16_t ring_size; 
    uint16_t nb_queues; 
};

#define RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID    (UINT16_MAX)

struct rte_eth_switch_info {
    const char *name;   
    uint16_t domain_id; 
    uint16_t port_id;
    uint16_t rx_domain;
};

struct rte_eth_rxseg_capa {
    __extension__
    uint32_t multi_pools:1; 
    uint32_t offset_allowed:1; 
    uint32_t offset_align_log2:4; 
    uint16_t max_nseg; 
    uint16_t reserved; 
};

enum rte_eth_representor_type {
    RTE_ETH_REPRESENTOR_NONE, 
    RTE_ETH_REPRESENTOR_VF,   
    RTE_ETH_REPRESENTOR_SF,   
    RTE_ETH_REPRESENTOR_PF,   
};

enum rte_eth_err_handle_mode {
    RTE_ETH_ERROR_HANDLE_MODE_NONE,
    RTE_ETH_ERROR_HANDLE_MODE_PASSIVE,
    RTE_ETH_ERROR_HANDLE_MODE_PROACTIVE,
};

struct rte_eth_dev_info {
    struct rte_device *device; 
    const char *driver_name; 
    unsigned int if_index; 
    uint16_t min_mtu;   
    uint16_t max_mtu;   
    const uint32_t *dev_flags; 
    uint32_t min_rx_bufsize; 
    uint32_t max_rx_pktlen; 
    uint32_t max_lro_pkt_size;
    uint16_t max_rx_queues; 
    uint16_t max_tx_queues; 
    uint32_t max_mac_addrs; 
    uint32_t max_hash_mac_addrs;
    uint16_t max_vfs; 
    uint16_t max_vmdq_pools; 
    struct rte_eth_rxseg_capa rx_seg_capa; 
    uint64_t rx_offload_capa;
    uint64_t tx_offload_capa;
    uint64_t rx_queue_offload_capa;
    uint64_t tx_queue_offload_capa;
    uint16_t reta_size;
    uint8_t hash_key_size; 
    uint64_t flow_type_rss_offloads;
    struct rte_eth_rxconf default_rxconf; 
    struct rte_eth_txconf default_txconf; 
    uint16_t vmdq_queue_base; 
    uint16_t vmdq_queue_num;  
    uint16_t vmdq_pool_base;  
    struct rte_eth_desc_lim rx_desc_lim;  
    struct rte_eth_desc_lim tx_desc_lim;  
    uint32_t speed_capa;  
    uint16_t nb_rx_queues; 
    uint16_t nb_tx_queues; 
    uint16_t max_rx_mempools;
    struct rte_eth_dev_portconf default_rxportconf;
    struct rte_eth_dev_portconf default_txportconf;
    uint64_t dev_capa;
    struct rte_eth_switch_info switch_info;
    enum rte_eth_err_handle_mode err_handle_mode;

    uint64_t reserved_64s[2]; 
    void *reserved_ptrs[2];   
};

#define RTE_ETH_QUEUE_STATE_STOPPED 0 
#define RTE_ETH_QUEUE_STATE_STARTED 1 
#define RTE_ETH_QUEUE_STATE_HAIRPIN 2 
struct rte_eth_rxq_info {
    struct rte_mempool *mp;     
    struct rte_eth_rxconf conf; 
    uint8_t scattered_rx;       
    uint8_t queue_state;        
    uint16_t nb_desc;           
    uint16_t rx_buf_size;       
    uint8_t avail_thresh;
} __rte_cache_min_aligned;

struct rte_eth_txq_info {
    struct rte_eth_txconf conf; 
    uint16_t nb_desc;           
    uint8_t queue_state;        
} __rte_cache_min_aligned;

/* Generic Burst mode flag definition, values can be ORed. */

#define RTE_ETH_BURST_FLAG_PER_QUEUE RTE_BIT64(0)

struct rte_eth_burst_mode {
    uint64_t flags; 
#define RTE_ETH_BURST_MODE_INFO_SIZE 1024 
    char info[RTE_ETH_BURST_MODE_INFO_SIZE]; 
};

#define RTE_ETH_XSTATS_NAME_SIZE 64

struct rte_eth_xstat {
    uint64_t id;        
    uint64_t value;     
};

struct rte_eth_xstat_name {
    char name[RTE_ETH_XSTATS_NAME_SIZE]; 
};

#define RTE_ETH_DCB_NUM_TCS    8
#define RTE_ETH_MAX_VMDQ_POOL  64

struct rte_eth_dcb_tc_queue_mapping {
    struct {
        uint16_t base;
        uint16_t nb_queue;
    } tc_rxq[RTE_ETH_MAX_VMDQ_POOL][RTE_ETH_DCB_NUM_TCS];
    struct {
        uint16_t base;
        uint16_t nb_queue;
    } tc_txq[RTE_ETH_MAX_VMDQ_POOL][RTE_ETH_DCB_NUM_TCS];
};

struct rte_eth_dcb_info {
    uint8_t nb_tcs;        
    uint8_t prio_tc[RTE_ETH_DCB_NUM_USER_PRIORITIES]; 
    uint8_t tc_bws[RTE_ETH_DCB_NUM_TCS]; 
    struct rte_eth_dcb_tc_queue_mapping tc_queue;
};

enum rte_eth_fec_mode {
    RTE_ETH_FEC_NOFEC = 0,      
    RTE_ETH_FEC_AUTO,       
    RTE_ETH_FEC_BASER,          
    RTE_ETH_FEC_RS,             
};

/* Translate from FEC mode to FEC capa */
#define RTE_ETH_FEC_MODE_TO_CAPA(x) RTE_BIT32(x)

/* This macro indicates FEC capa mask */
#define RTE_ETH_FEC_MODE_CAPA_MASK(x) RTE_BIT32(RTE_ETH_FEC_ ## x)

/* A structure used to get capabilities per link speed */
struct rte_eth_fec_capa {
    uint32_t speed; 
    uint32_t capa;  
};

#define RTE_ETH_ALL RTE_MAX_ETHPORTS

/* Macros to check for valid port */
#define RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, retval) do { \
    if (!rte_eth_dev_is_valid_port(port_id)) { \
        RTE_ETHDEV_LOG(ERR, "Invalid port_id=%u\n", port_id); \
        return retval; \
    } \
} while (0)

#define RTE_ETH_VALID_PORTID_OR_RET(port_id) do { \
    if (!rte_eth_dev_is_valid_port(port_id)) { \
        RTE_ETHDEV_LOG(ERR, "Invalid port_id=%u\n", port_id); \
        return; \
    } \
} while (0)

typedef uint16_t (*rte_rx_callback_fn)(uint16_t port_id, uint16_t queue,
    struct rte_mbuf *pkts[], uint16_t nb_pkts, uint16_t max_pkts,
    void *user_param);

typedef uint16_t (*rte_tx_callback_fn)(uint16_t port_id, uint16_t queue,
    struct rte_mbuf *pkts[], uint16_t nb_pkts, void *user_param);

enum rte_eth_dev_state {
    RTE_ETH_DEV_UNUSED = 0,
    RTE_ETH_DEV_ATTACHED,
    RTE_ETH_DEV_REMOVED,
};

struct rte_eth_dev_sriov {
    uint8_t active;               
    uint8_t nb_q_per_pool;        
    uint16_t def_vmdq_idx;        
    uint16_t def_pool_q_idx;      
};
#define RTE_ETH_DEV_SRIOV(dev)         ((dev)->data->sriov)

#define RTE_ETH_NAME_MAX_LEN RTE_DEV_NAME_MAX_LEN

#define RTE_ETH_DEV_NO_OWNER 0

#define RTE_ETH_MAX_OWNER_NAME_LEN 64

struct rte_eth_dev_owner {
    uint64_t id; 
    char name[RTE_ETH_MAX_OWNER_NAME_LEN]; 
};

#define RTE_ETH_DEV_FLOW_OPS_THREAD_SAFE  RTE_BIT32(0)

#define RTE_ETH_DEV_INTR_LSC              RTE_BIT32(1)

#define RTE_ETH_DEV_BONDED_SLAVE          RTE_BIT32(2)

#define RTE_ETH_DEV_INTR_RMV              RTE_BIT32(3)

#define RTE_ETH_DEV_REPRESENTOR           RTE_BIT32(4)

#define RTE_ETH_DEV_NOLIVE_MAC_ADDR       RTE_BIT32(5)

#define RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS RTE_BIT32(6)

uint64_t rte_eth_find_next_owned_by(uint16_t port_id,
        const uint64_t owner_id);

#define RTE_ETH_FOREACH_DEV_OWNED_BY(p, o) \
    for (p = rte_eth_find_next_owned_by(0, o); \
         (unsigned int)p < (unsigned int)RTE_MAX_ETHPORTS; \
         p = rte_eth_find_next_owned_by(p + 1, o))

uint16_t rte_eth_find_next(uint16_t port_id);

#define RTE_ETH_FOREACH_DEV(p) \
    RTE_ETH_FOREACH_DEV_OWNED_BY(p, RTE_ETH_DEV_NO_OWNER)

uint16_t
rte_eth_find_next_of(uint16_t port_id_start,
        const struct rte_device *parent);

#define RTE_ETH_FOREACH_DEV_OF(port_id, parent) \
    for (port_id = rte_eth_find_next_of(0, parent); \
        port_id < RTE_MAX_ETHPORTS; \
        port_id = rte_eth_find_next_of(port_id + 1, parent))

uint16_t
rte_eth_find_next_sibling(uint16_t port_id_start, uint16_t ref_port_id);

#define RTE_ETH_FOREACH_DEV_SIBLING(port_id, ref_port_id) \
    for (port_id = rte_eth_find_next_sibling(0, ref_port_id); \
        port_id < RTE_MAX_ETHPORTS; \
        port_id = rte_eth_find_next_sibling(port_id + 1, ref_port_id))

int rte_eth_dev_owner_new(uint64_t *owner_id);

int rte_eth_dev_owner_set(const uint16_t port_id,
        const struct rte_eth_dev_owner *owner);

int rte_eth_dev_owner_unset(const uint16_t port_id,
        const uint64_t owner_id);

int rte_eth_dev_owner_delete(const uint64_t owner_id);

int rte_eth_dev_owner_get(const uint16_t port_id,
        struct rte_eth_dev_owner *owner);

uint16_t rte_eth_dev_count_avail(void);

uint16_t rte_eth_dev_count_total(void);

uint32_t rte_eth_speed_bitflag(uint32_t speed, int duplex);

const char *rte_eth_dev_rx_offload_name(uint64_t offload);

const char *rte_eth_dev_tx_offload_name(uint64_t offload);

__rte_experimental
const char *rte_eth_dev_capability_name(uint64_t capability);

int rte_eth_dev_configure(uint16_t port_id, uint16_t nb_rx_queue,
        uint16_t nb_tx_queue, const struct rte_eth_conf *eth_conf);

int
rte_eth_dev_is_removed(uint16_t port_id);

int rte_eth_rx_queue_setup(uint16_t port_id, uint16_t rx_queue_id,
        uint16_t nb_rx_desc, unsigned int socket_id,
        const struct rte_eth_rxconf *rx_conf,
        struct rte_mempool *mb_pool);

__rte_experimental
int rte_eth_rx_hairpin_queue_setup
    (uint16_t port_id, uint16_t rx_queue_id, uint16_t nb_rx_desc,
     const struct rte_eth_hairpin_conf *conf);

int rte_eth_tx_queue_setup(uint16_t port_id, uint16_t tx_queue_id,
        uint16_t nb_tx_desc, unsigned int socket_id,
        const struct rte_eth_txconf *tx_conf);

__rte_experimental
int rte_eth_tx_hairpin_queue_setup
    (uint16_t port_id, uint16_t tx_queue_id, uint16_t nb_tx_desc,
     const struct rte_eth_hairpin_conf *conf);

__rte_experimental
int rte_eth_hairpin_get_peer_ports(uint16_t port_id, uint16_t *peer_ports,
                   size_t len, uint32_t direction);

__rte_experimental
int rte_eth_hairpin_bind(uint16_t tx_port, uint16_t rx_port);

__rte_experimental
int rte_eth_hairpin_unbind(uint16_t tx_port, uint16_t rx_port);

__rte_experimental
int rte_eth_dev_count_aggr_ports(uint16_t port_id);

__rte_experimental
int rte_eth_dev_map_aggr_tx_affinity(uint16_t port_id, uint16_t tx_queue_id,
                     uint8_t affinity);

int rte_eth_dev_socket_id(uint16_t port_id);

int rte_eth_dev_is_valid_port(uint16_t port_id);

int rte_eth_dev_rx_queue_start(uint16_t port_id, uint16_t rx_queue_id);

int rte_eth_dev_rx_queue_stop(uint16_t port_id, uint16_t rx_queue_id);

int rte_eth_dev_tx_queue_start(uint16_t port_id, uint16_t tx_queue_id);

int rte_eth_dev_tx_queue_stop(uint16_t port_id, uint16_t tx_queue_id);

int rte_eth_dev_start(uint16_t port_id);

int rte_eth_dev_stop(uint16_t port_id);

int rte_eth_dev_set_link_up(uint16_t port_id);

int rte_eth_dev_set_link_down(uint16_t port_id);

int rte_eth_dev_close(uint16_t port_id);

int rte_eth_dev_reset(uint16_t port_id);

int rte_eth_promiscuous_enable(uint16_t port_id);

int rte_eth_promiscuous_disable(uint16_t port_id);

int rte_eth_promiscuous_get(uint16_t port_id);

int rte_eth_allmulticast_enable(uint16_t port_id);

int rte_eth_allmulticast_disable(uint16_t port_id);

int rte_eth_allmulticast_get(uint16_t port_id);

int rte_eth_link_get(uint16_t port_id, struct rte_eth_link *link);

int rte_eth_link_get_nowait(uint16_t port_id, struct rte_eth_link *link);

__rte_experimental
const char *rte_eth_link_speed_to_str(uint32_t link_speed);

__rte_experimental
int rte_eth_link_to_str(char *str, size_t len,
            const struct rte_eth_link *eth_link);

int rte_eth_stats_get(uint16_t port_id, struct rte_eth_stats *stats);

int rte_eth_stats_reset(uint16_t port_id);

int rte_eth_xstats_get_names(uint16_t port_id,
        struct rte_eth_xstat_name *xstats_names,
        unsigned int size);

int rte_eth_xstats_get(uint16_t port_id, struct rte_eth_xstat *xstats,
        unsigned int n);

int
rte_eth_xstats_get_names_by_id(uint16_t port_id,
    struct rte_eth_xstat_name *xstats_names, unsigned int size,
    uint64_t *ids);

int rte_eth_xstats_get_by_id(uint16_t port_id, const uint64_t *ids,
                 uint64_t *values, unsigned int size);

int rte_eth_xstats_get_id_by_name(uint16_t port_id, const char *xstat_name,
        uint64_t *id);

int rte_eth_xstats_reset(uint16_t port_id);

int rte_eth_dev_set_tx_queue_stats_mapping(uint16_t port_id,
        uint16_t tx_queue_id, uint8_t stat_idx);

int rte_eth_dev_set_rx_queue_stats_mapping(uint16_t port_id,
                       uint16_t rx_queue_id,
                       uint8_t stat_idx);

int rte_eth_macaddr_get(uint16_t port_id, struct rte_ether_addr *mac_addr);

__rte_experimental
int rte_eth_macaddrs_get(uint16_t port_id, struct rte_ether_addr *ma,
    unsigned int num);

int rte_eth_dev_info_get(uint16_t port_id, struct rte_eth_dev_info *dev_info);

__rte_experimental
int rte_eth_dev_conf_get(uint16_t port_id, struct rte_eth_conf *dev_conf);

int rte_eth_dev_fw_version_get(uint16_t port_id,
                   char *fw_version, size_t fw_size);

int rte_eth_dev_get_supported_ptypes(uint16_t port_id, uint32_t ptype_mask,
                     uint32_t *ptypes, int num);
int rte_eth_dev_set_ptypes(uint16_t port_id, uint32_t ptype_mask,
               uint32_t *set_ptypes, unsigned int num);

int rte_eth_dev_get_mtu(uint16_t port_id, uint16_t *mtu);

int rte_eth_dev_set_mtu(uint16_t port_id, uint16_t mtu);

int rte_eth_dev_vlan_filter(uint16_t port_id, uint16_t vlan_id, int on);

int rte_eth_dev_set_vlan_strip_on_queue(uint16_t port_id, uint16_t rx_queue_id,
        int on);

int rte_eth_dev_set_vlan_ether_type(uint16_t port_id,
                    enum rte_vlan_type vlan_type,
                    uint16_t tag_type);

int rte_eth_dev_set_vlan_offload(uint16_t port_id, int offload_mask);

int rte_eth_dev_get_vlan_offload(uint16_t port_id);

int rte_eth_dev_set_vlan_pvid(uint16_t port_id, uint16_t pvid, int on);

__rte_experimental
int rte_eth_rx_avail_thresh_set(uint16_t port_id, uint16_t queue_id,
                   uint8_t avail_thresh);

__rte_experimental
int rte_eth_rx_avail_thresh_query(uint16_t port_id, uint16_t *queue_id,
                 uint8_t *avail_thresh);

typedef void (*buffer_tx_error_fn)(struct rte_mbuf **unsent, uint16_t count,
        void *userdata);

struct rte_eth_dev_tx_buffer {
    buffer_tx_error_fn error_callback;
    void *error_userdata;
    uint16_t size;           
    uint16_t length;         
    struct rte_mbuf *pkts[];
};

#define RTE_ETH_TX_BUFFER_SIZE(sz) \
    (sizeof(struct rte_eth_dev_tx_buffer) + (sz) * sizeof(struct rte_mbuf *))

int
rte_eth_tx_buffer_init(struct rte_eth_dev_tx_buffer *buffer, uint16_t size);

int
rte_eth_tx_buffer_set_err_callback(struct rte_eth_dev_tx_buffer *buffer,
        buffer_tx_error_fn callback, void *userdata);

void
rte_eth_tx_buffer_drop_callback(struct rte_mbuf **pkts, uint16_t unsent,
        void *userdata);

void
rte_eth_tx_buffer_count_callback(struct rte_mbuf **pkts, uint16_t unsent,
        void *userdata);

int
rte_eth_tx_done_cleanup(uint16_t port_id, uint16_t queue_id, uint32_t free_cnt);

enum rte_eth_event_macsec_subtype {
    RTE_ETH_SUBEVENT_MACSEC_UNKNOWN,
    RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_V_EQ1,
    RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_E_EQ0_C_EQ1,
    RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_SL_GTE48,
    RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_ES_EQ1_SC_EQ1,
    RTE_ETH_SUBEVENT_MACSEC_RX_SECTAG_SC_EQ1_SCB_EQ1,
};

enum rte_eth_event_macsec_type {
    RTE_ETH_EVENT_MACSEC_UNKNOWN,
    RTE_ETH_EVENT_MACSEC_SECTAG_VAL_ERR,
    RTE_ETH_EVENT_MACSEC_RX_SA_PN_HARD_EXP,
    RTE_ETH_EVENT_MACSEC_RX_SA_PN_SOFT_EXP,
    RTE_ETH_EVENT_MACSEC_TX_SA_PN_HARD_EXP,
    RTE_ETH_EVENT_MACSEC_TX_SA_PN_SOFT_EXP,
    RTE_ETH_EVENT_MACSEC_SA_NOT_VALID,
};

struct rte_eth_event_macsec_desc {
    enum rte_eth_event_macsec_type type;
    enum rte_eth_event_macsec_subtype subtype;
    uint64_t metadata;
};

enum rte_eth_event_ipsec_subtype {
    RTE_ETH_EVENT_IPSEC_UNKNOWN = 0,
    RTE_ETH_EVENT_IPSEC_ESN_OVERFLOW,
    RTE_ETH_EVENT_IPSEC_SA_TIME_EXPIRY,
    RTE_ETH_EVENT_IPSEC_SA_BYTE_EXPIRY,
    RTE_ETH_EVENT_IPSEC_SA_PKT_EXPIRY,
    RTE_ETH_EVENT_IPSEC_SA_BYTE_HARD_EXPIRY,
    RTE_ETH_EVENT_IPSEC_SA_PKT_HARD_EXPIRY,
    RTE_ETH_EVENT_IPSEC_MAX
};

struct rte_eth_event_ipsec_desc {
    enum rte_eth_event_ipsec_subtype subtype;
    uint64_t metadata;
};

enum rte_eth_event_type {
    RTE_ETH_EVENT_UNKNOWN,  
    RTE_ETH_EVENT_INTR_LSC, 
    RTE_ETH_EVENT_QUEUE_STATE,
    RTE_ETH_EVENT_INTR_RESET,
    RTE_ETH_EVENT_VF_MBOX,  
    RTE_ETH_EVENT_MACSEC,   
    RTE_ETH_EVENT_INTR_RMV, 
    RTE_ETH_EVENT_NEW,      
    RTE_ETH_EVENT_DESTROY,  
    RTE_ETH_EVENT_IPSEC,    
    RTE_ETH_EVENT_FLOW_AGED,
    RTE_ETH_EVENT_RX_AVAIL_THRESH,
    RTE_ETH_EVENT_ERR_RECOVERING,
    RTE_ETH_EVENT_RECOVERY_SUCCESS,
    RTE_ETH_EVENT_RECOVERY_FAILED,
    RTE_ETH_EVENT_MAX       
};

typedef int (*rte_eth_dev_cb_fn)(uint16_t port_id,
        enum rte_eth_event_type event, void *cb_arg, void *ret_param);

int rte_eth_dev_callback_register(uint16_t port_id,
            enum rte_eth_event_type event,
        rte_eth_dev_cb_fn cb_fn, void *cb_arg);

int rte_eth_dev_callback_unregister(uint16_t port_id,
            enum rte_eth_event_type event,
        rte_eth_dev_cb_fn cb_fn, void *cb_arg);

int rte_eth_dev_rx_intr_enable(uint16_t port_id, uint16_t queue_id);

int rte_eth_dev_rx_intr_disable(uint16_t port_id, uint16_t queue_id);

int rte_eth_dev_rx_intr_ctl(uint16_t port_id, int epfd, int op, void *data);

int rte_eth_dev_rx_intr_ctl_q(uint16_t port_id, uint16_t queue_id,
                  int epfd, int op, void *data);

int
rte_eth_dev_rx_intr_ctl_q_get_fd(uint16_t port_id, uint16_t queue_id);

int  rte_eth_led_on(uint16_t port_id);

int  rte_eth_led_off(uint16_t port_id);

__rte_experimental
int rte_eth_fec_get_capability(uint16_t port_id,
                   struct rte_eth_fec_capa *speed_fec_capa,
                   unsigned int num);

__rte_experimental
int rte_eth_fec_get(uint16_t port_id, uint32_t *fec_capa);

__rte_experimental
int rte_eth_fec_set(uint16_t port_id, uint32_t fec_capa);

int rte_eth_dev_flow_ctrl_get(uint16_t port_id,
                  struct rte_eth_fc_conf *fc_conf);

int rte_eth_dev_flow_ctrl_set(uint16_t port_id,
                  struct rte_eth_fc_conf *fc_conf);

int rte_eth_dev_priority_flow_ctrl_set(uint16_t port_id,
                struct rte_eth_pfc_conf *pfc_conf);

int rte_eth_dev_mac_addr_add(uint16_t port_id, struct rte_ether_addr *mac_addr,
                uint32_t pool);

__rte_experimental
int rte_eth_dev_priority_flow_ctrl_queue_info_get(uint16_t port_id,
        struct rte_eth_pfc_queue_info *pfc_queue_info);

__rte_experimental
int rte_eth_dev_priority_flow_ctrl_queue_configure(uint16_t port_id,
        struct rte_eth_pfc_queue_conf *pfc_queue_conf);

int rte_eth_dev_mac_addr_remove(uint16_t port_id,
                struct rte_ether_addr *mac_addr);

int rte_eth_dev_default_mac_addr_set(uint16_t port_id,
        struct rte_ether_addr *mac_addr);

int rte_eth_dev_rss_reta_update(uint16_t port_id,
                struct rte_eth_rss_reta_entry64 *reta_conf,
                uint16_t reta_size);

int rte_eth_dev_rss_reta_query(uint16_t port_id,
                   struct rte_eth_rss_reta_entry64 *reta_conf,
                   uint16_t reta_size);

int rte_eth_dev_uc_hash_table_set(uint16_t port_id, struct rte_ether_addr *addr,
                  uint8_t on);

int rte_eth_dev_uc_all_hash_table_set(uint16_t port_id, uint8_t on);

int rte_eth_set_queue_rate_limit(uint16_t port_id, uint16_t queue_idx,
            uint32_t tx_rate);

int rte_eth_dev_rss_hash_update(uint16_t port_id,
                struct rte_eth_rss_conf *rss_conf);

int
rte_eth_dev_rss_hash_conf_get(uint16_t port_id,
                  struct rte_eth_rss_conf *rss_conf);

int
rte_eth_dev_udp_tunnel_port_add(uint16_t port_id,
                struct rte_eth_udp_tunnel *tunnel_udp);

int
rte_eth_dev_udp_tunnel_port_delete(uint16_t port_id,
                   struct rte_eth_udp_tunnel *tunnel_udp);

int rte_eth_dev_get_dcb_info(uint16_t port_id,
                 struct rte_eth_dcb_info *dcb_info);

struct rte_eth_rxtx_callback;

const struct rte_eth_rxtx_callback *
rte_eth_add_rx_callback(uint16_t port_id, uint16_t queue_id,
        rte_rx_callback_fn fn, void *user_param);

const struct rte_eth_rxtx_callback *
rte_eth_add_first_rx_callback(uint16_t port_id, uint16_t queue_id,
        rte_rx_callback_fn fn, void *user_param);

const struct rte_eth_rxtx_callback *
rte_eth_add_tx_callback(uint16_t port_id, uint16_t queue_id,
        rte_tx_callback_fn fn, void *user_param);

int rte_eth_remove_rx_callback(uint16_t port_id, uint16_t queue_id,
        const struct rte_eth_rxtx_callback *user_cb);

int rte_eth_remove_tx_callback(uint16_t port_id, uint16_t queue_id,
        const struct rte_eth_rxtx_callback *user_cb);

int rte_eth_rx_queue_info_get(uint16_t port_id, uint16_t queue_id,
    struct rte_eth_rxq_info *qinfo);

int rte_eth_tx_queue_info_get(uint16_t port_id, uint16_t queue_id,
    struct rte_eth_txq_info *qinfo);

int rte_eth_rx_burst_mode_get(uint16_t port_id, uint16_t queue_id,
    struct rte_eth_burst_mode *mode);

int rte_eth_tx_burst_mode_get(uint16_t port_id, uint16_t queue_id,
    struct rte_eth_burst_mode *mode);

__rte_experimental
int rte_eth_get_monitor_addr(uint16_t port_id, uint16_t queue_id,
        struct rte_power_monitor_cond *pmc);

int rte_eth_dev_get_reg_info(uint16_t port_id, struct rte_dev_reg_info *info);

int rte_eth_dev_get_eeprom_length(uint16_t port_id);

int rte_eth_dev_get_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info);

int rte_eth_dev_set_eeprom(uint16_t port_id, struct rte_dev_eeprom_info *info);

__rte_experimental
int
rte_eth_dev_get_module_info(uint16_t port_id,
                struct rte_eth_dev_module_info *modinfo);

__rte_experimental
int
rte_eth_dev_get_module_eeprom(uint16_t port_id,
                  struct rte_dev_eeprom_info *info);

int rte_eth_dev_set_mc_addr_list(uint16_t port_id,
                 struct rte_ether_addr *mc_addr_set,
                 uint32_t nb_mc_addr);

int rte_eth_timesync_enable(uint16_t port_id);

int rte_eth_timesync_disable(uint16_t port_id);

int rte_eth_timesync_read_rx_timestamp(uint16_t port_id,
        struct timespec *timestamp, uint32_t flags);

int rte_eth_timesync_read_tx_timestamp(uint16_t port_id,
        struct timespec *timestamp);

int rte_eth_timesync_adjust_time(uint16_t port_id, int64_t delta);

int rte_eth_timesync_read_time(uint16_t port_id, struct timespec *time);

int rte_eth_timesync_write_time(uint16_t port_id, const struct timespec *time);

__rte_experimental
int
rte_eth_read_clock(uint16_t port_id, uint64_t *clock);

int
rte_eth_dev_get_port_by_name(const char *name, uint16_t *port_id);

int
rte_eth_dev_get_name_by_port(uint16_t port_id, char *name);

int rte_eth_dev_adjust_nb_rx_tx_desc(uint16_t port_id,
                     uint16_t *nb_rx_desc,
                     uint16_t *nb_tx_desc);

int
rte_eth_dev_pool_ops_supported(uint16_t port_id, const char *pool);

void *
rte_eth_dev_get_sec_ctx(uint16_t port_id);

__rte_experimental
int rte_eth_dev_hairpin_capability_get(uint16_t port_id,
                       struct rte_eth_hairpin_cap *cap);

struct rte_eth_representor_range {
    enum rte_eth_representor_type type; 
    int controller; 
    int pf; 
    __extension__
    union {
        int vf; 
        int sf; 
    };
    uint32_t id_base; 
    uint32_t id_end;  
    char name[RTE_DEV_NAME_MAX_LEN]; 
};

struct rte_eth_representor_info {
    uint16_t controller; 
    uint16_t pf; 
    uint32_t nb_ranges_alloc; 
    uint32_t nb_ranges; 
    struct rte_eth_representor_range ranges[];
};

__rte_experimental
int rte_eth_representor_info_get(uint16_t port_id,
                 struct rte_eth_representor_info *info);

#define RTE_ETH_RX_METADATA_USER_FLAG RTE_BIT64(0)

#define RTE_ETH_RX_METADATA_USER_MARK RTE_BIT64(1)

#define RTE_ETH_RX_METADATA_TUNNEL_ID RTE_BIT64(2)

int rte_eth_rx_metadata_negotiate(uint16_t port_id, uint64_t *features);

#define RTE_ETH_DEV_REASSEMBLY_F_IPV4 (RTE_BIT32(0))

#define RTE_ETH_DEV_REASSEMBLY_F_IPV6 (RTE_BIT32(1))

struct rte_eth_ip_reassembly_params {
    uint32_t timeout_ms;
    uint16_t max_frags;
    uint16_t flags;
};

__rte_experimental
int rte_eth_ip_reassembly_capability_get(uint16_t port_id,
        struct rte_eth_ip_reassembly_params *capa);

__rte_experimental
int rte_eth_ip_reassembly_conf_get(uint16_t port_id,
        struct rte_eth_ip_reassembly_params *conf);

__rte_experimental
int rte_eth_ip_reassembly_conf_set(uint16_t port_id,
        const struct rte_eth_ip_reassembly_params *conf);

typedef struct {
    struct rte_mbuf *next_frag;
    uint16_t time_spent;
    uint16_t nb_frags;
} rte_eth_ip_reassembly_dynfield_t;

__rte_experimental
int rte_eth_dev_priv_dump(uint16_t port_id, FILE *file);

__rte_experimental
int rte_eth_rx_descriptor_dump(uint16_t port_id, uint16_t queue_id,
                   uint16_t offset, uint16_t num, FILE *file);

__rte_experimental
int rte_eth_tx_descriptor_dump(uint16_t port_id, uint16_t queue_id,
                   uint16_t offset, uint16_t num, FILE *file);


/* Congestion management */

enum rte_eth_cman_obj {
    RTE_ETH_CMAN_OBJ_RX_QUEUE = RTE_BIT32(0),
    RTE_ETH_CMAN_OBJ_RX_QUEUE_MEMPOOL = RTE_BIT32(1),
};

struct rte_eth_cman_info {
    uint64_t modes_supported;
    uint64_t objs_supported;
    uint8_t rsvd[8];
};

struct rte_eth_cman_config {
    enum rte_eth_cman_obj obj;
    enum rte_cman_mode mode;
    union {
        uint16_t rx_queue;
        uint8_t rsvd_obj_params[4];
    } obj_param;
    union {
        struct rte_cman_red_params red;
        uint8_t rsvd_mode_params[4];
    } mode_param;
};

__rte_experimental
int rte_eth_cman_info_get(uint16_t port_id, struct rte_eth_cman_info *info);

__rte_experimental
int rte_eth_cman_config_init(uint16_t port_id, struct rte_eth_cman_config *config);

__rte_experimental
int rte_eth_cman_config_set(uint16_t port_id, const struct rte_eth_cman_config *config);

__rte_experimental
int rte_eth_cman_config_get(uint16_t port_id, struct rte_eth_cman_config *config);

#include <rte_ethdev_core.h>

uint16_t rte_eth_call_rx_callbacks(uint16_t port_id, uint16_t queue_id,
        struct rte_mbuf **rx_pkts, uint16_t nb_rx, uint16_t nb_pkts,
        void *opaque);

static inline uint16_t
rte_eth_rx_burst(uint16_t port_id, uint16_t queue_id,
         struct rte_mbuf **rx_pkts, const uint16_t nb_pkts)
{
    uint16_t nb_rx;
    struct rte_eth_fp_ops *p;
    void *qd;

#ifdef RTE_ETHDEV_DEBUG_RX
    if (port_id >= RTE_MAX_ETHPORTS ||
            queue_id >= RTE_MAX_QUEUES_PER_PORT) {
        RTE_ETHDEV_LOG(ERR,
            "Invalid port_id=%u or queue_id=%u\n",
            port_id, queue_id);
        return 0;
    }
#endif

    /* fetch pointer to queue data */
    p = &rte_eth_fp_ops[port_id];
    qd = p->rxq.data[queue_id];

#ifdef RTE_ETHDEV_DEBUG_RX
    RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);

    if (qd == NULL) {
        RTE_ETHDEV_LOG(ERR, "Invalid Rx queue_id=%u for port_id=%u\n",
            queue_id, port_id);
        return 0;
    }
#endif

    nb_rx = p->rx_pkt_burst(qd, rx_pkts, nb_pkts);

#ifdef RTE_ETHDEV_RXTX_CALLBACKS
    {
        void *cb;

        /* __ATOMIC_RELEASE memory order was used when the
         * call back was inserted into the list.
         * Since there is a clear dependency between loading
         * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is
         * not required.
         */
        cb = __atomic_load_n((void **)&p->rxq.clbk[queue_id],
                __ATOMIC_RELAXED);
        if (unlikely(cb != NULL))
            nb_rx = rte_eth_call_rx_callbacks(port_id, queue_id,
                    rx_pkts, nb_rx, nb_pkts, cb);
    }
#endif

    rte_ethdev_trace_rx_burst(port_id, queue_id, (void **)rx_pkts, nb_rx);
    return nb_rx;
}

static inline int
rte_eth_rx_queue_count(uint16_t port_id, uint16_t queue_id)
{
    struct rte_eth_fp_ops *p;
    void *qd;

#ifdef RTE_ETHDEV_DEBUG_RX
    if (port_id >= RTE_MAX_ETHPORTS ||
            queue_id >= RTE_MAX_QUEUES_PER_PORT) {
        RTE_ETHDEV_LOG(ERR,
            "Invalid port_id=%u or queue_id=%u\n",
            port_id, queue_id);
        return -EINVAL;
    }
#endif

    /* fetch pointer to queue data */
    p = &rte_eth_fp_ops[port_id];
    qd = p->rxq.data[queue_id];

#ifdef RTE_ETHDEV_DEBUG_RX
    RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
    if (qd == NULL)
        return -EINVAL;
#endif

    if (*p->rx_queue_count == NULL)
        return -ENOTSUP;
    return (int)(*p->rx_queue_count)(qd);
}

#define RTE_ETH_RX_DESC_AVAIL    0 
#define RTE_ETH_RX_DESC_DONE     1 
#define RTE_ETH_RX_DESC_UNAVAIL  2 
static inline int
rte_eth_rx_descriptor_status(uint16_t port_id, uint16_t queue_id,
    uint16_t offset)
{
    struct rte_eth_fp_ops *p;
    void *qd;

#ifdef RTE_ETHDEV_DEBUG_RX
    if (port_id >= RTE_MAX_ETHPORTS ||
            queue_id >= RTE_MAX_QUEUES_PER_PORT) {
        RTE_ETHDEV_LOG(ERR,
            "Invalid port_id=%u or queue_id=%u\n",
            port_id, queue_id);
        return -EINVAL;
    }
#endif

    /* fetch pointer to queue data */
    p = &rte_eth_fp_ops[port_id];
    qd = p->rxq.data[queue_id];

#ifdef RTE_ETHDEV_DEBUG_RX
    RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
    if (qd == NULL)
        return -ENODEV;
#endif
    if (*p->rx_descriptor_status == NULL)
        return -ENOTSUP;
    return (*p->rx_descriptor_status)(qd, offset);
}

#define RTE_ETH_TX_DESC_FULL    0 
#define RTE_ETH_TX_DESC_DONE    1 
#define RTE_ETH_TX_DESC_UNAVAIL 2 
static inline int rte_eth_tx_descriptor_status(uint16_t port_id,
    uint16_t queue_id, uint16_t offset)
{
    struct rte_eth_fp_ops *p;
    void *qd;

#ifdef RTE_ETHDEV_DEBUG_TX
    if (port_id >= RTE_MAX_ETHPORTS ||
            queue_id >= RTE_MAX_QUEUES_PER_PORT) {
        RTE_ETHDEV_LOG(ERR,
            "Invalid port_id=%u or queue_id=%u\n",
            port_id, queue_id);
        return -EINVAL;
    }
#endif

    /* fetch pointer to queue data */
    p = &rte_eth_fp_ops[port_id];
    qd = p->txq.data[queue_id];

#ifdef RTE_ETHDEV_DEBUG_TX
    RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
    if (qd == NULL)
        return -ENODEV;
#endif
    if (*p->tx_descriptor_status == NULL)
        return -ENOTSUP;
    return (*p->tx_descriptor_status)(qd, offset);
}

uint16_t rte_eth_call_tx_callbacks(uint16_t port_id, uint16_t queue_id,
    struct rte_mbuf **tx_pkts, uint16_t nb_pkts, void *opaque);

static inline uint16_t
rte_eth_tx_burst(uint16_t port_id, uint16_t queue_id,
         struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
{
    struct rte_eth_fp_ops *p;
    void *qd;

#ifdef RTE_ETHDEV_DEBUG_TX
    if (port_id >= RTE_MAX_ETHPORTS ||
            queue_id >= RTE_MAX_QUEUES_PER_PORT) {
        RTE_ETHDEV_LOG(ERR,
            "Invalid port_id=%u or queue_id=%u\n",
            port_id, queue_id);
        return 0;
    }
#endif

    /* fetch pointer to queue data */
    p = &rte_eth_fp_ops[port_id];
    qd = p->txq.data[queue_id];

#ifdef RTE_ETHDEV_DEBUG_TX
    RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);

    if (qd == NULL) {
        RTE_ETHDEV_LOG(ERR, "Invalid Tx queue_id=%u for port_id=%u\n",
            queue_id, port_id);
        return 0;
    }
#endif

#ifdef RTE_ETHDEV_RXTX_CALLBACKS
    {
        void *cb;

        /* __ATOMIC_RELEASE memory order was used when the
         * call back was inserted into the list.
         * Since there is a clear dependency between loading
         * cb and cb->fn/cb->next, __ATOMIC_ACQUIRE memory order is
         * not required.
         */
        cb = __atomic_load_n((void **)&p->txq.clbk[queue_id],
                __ATOMIC_RELAXED);
        if (unlikely(cb != NULL))
            nb_pkts = rte_eth_call_tx_callbacks(port_id, queue_id,
                    tx_pkts, nb_pkts, cb);
    }
#endif

    nb_pkts = p->tx_pkt_burst(qd, tx_pkts, nb_pkts);

    rte_ethdev_trace_tx_burst(port_id, queue_id, (void **)tx_pkts, nb_pkts);
    return nb_pkts;
}

#ifndef RTE_ETHDEV_TX_PREPARE_NOOP

static inline uint16_t
rte_eth_tx_prepare(uint16_t port_id, uint16_t queue_id,
        struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
{
    struct rte_eth_fp_ops *p;
    void *qd;

#ifdef RTE_ETHDEV_DEBUG_TX
    if (port_id >= RTE_MAX_ETHPORTS ||
            queue_id >= RTE_MAX_QUEUES_PER_PORT) {
        RTE_ETHDEV_LOG(ERR,
            "Invalid port_id=%u or queue_id=%u\n",
            port_id, queue_id);
        rte_errno = ENODEV;
        return 0;
    }
#endif

    /* fetch pointer to queue data */
    p = &rte_eth_fp_ops[port_id];
    qd = p->txq.data[queue_id];

#ifdef RTE_ETHDEV_DEBUG_TX
    if (!rte_eth_dev_is_valid_port(port_id)) {
        RTE_ETHDEV_LOG(ERR, "Invalid Tx port_id=%u\n", port_id);
        rte_errno = ENODEV;
        return 0;
    }
    if (qd == NULL) {
        RTE_ETHDEV_LOG(ERR, "Invalid Tx queue_id=%u for port_id=%u\n",
            queue_id, port_id);
        rte_errno = EINVAL;
        return 0;
    }
#endif

    if (!p->tx_pkt_prepare)
        return nb_pkts;

    return p->tx_pkt_prepare(qd, tx_pkts, nb_pkts);
}

#else

/*
 * Native NOOP operation for compilation targets which doesn't require any
 * preparations steps, and functional NOOP may introduce unnecessary performance
 * drop.
 *
 * Generally this is not a good idea to turn it on globally and didn't should
 * be used if behavior of tx_preparation can change.
 */

static inline uint16_t
rte_eth_tx_prepare(__rte_unused uint16_t port_id,
        __rte_unused uint16_t queue_id,
        __rte_unused struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
{
    return nb_pkts;
}

#endif

static inline uint16_t
rte_eth_tx_buffer_flush(uint16_t port_id, uint16_t queue_id,
        struct rte_eth_dev_tx_buffer *buffer)
{
    uint16_t sent;
    uint16_t to_send = buffer->length;

    if (to_send == 0)
        return 0;

    sent = rte_eth_tx_burst(port_id, queue_id, buffer->pkts, to_send);

    buffer->length = 0;

    /* All packets sent, or to be dealt with by callback below */
    if (unlikely(sent != to_send))
        buffer->error_callback(&buffer->pkts[sent],
                       (uint16_t)(to_send - sent),
                       buffer->error_userdata);

    return sent;
}

static __rte_always_inline uint16_t
rte_eth_tx_buffer(uint16_t port_id, uint16_t queue_id,
        struct rte_eth_dev_tx_buffer *buffer, struct rte_mbuf *tx_pkt)
{
    buffer->pkts[buffer->length++] = tx_pkt;
    if (buffer->length < buffer->size)
        return 0;

    return rte_eth_tx_buffer_flush(port_id, queue_id, buffer);
}

__rte_experimental
int rte_eth_buffer_split_get_supported_hdr_ptypes(uint16_t port_id, uint32_t *ptypes, int num);

#ifdef __cplusplus
}
#endif

#endif /* _RTE_ETHDEV_H_ */