rte_gpudev.h

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/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright (c) 2021 NVIDIA Corporation & Affiliates
 */
 
#ifndef RTE_GPUDEV_H
#define RTE_GPUDEV_H
 
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
 
#include <rte_mbuf.h>
#include <rte_bitops.h>
#include <rte_compat.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define RTE_GPU_DEFAULT_MAX 32
 
#define RTE_GPU_ID_NONE -1
#define RTE_GPU_ID_ANY INT16_MIN
 
#define RTE_GPU_CALLBACK_ANY_DATA ((void *)-1)
 
#define RTE_GPU_VOLATILE(x) (*(volatile typeof(x) *)&(x))
 
#define RTE_GPU_COMM_LIST_PKTS_MAX 1024
 
struct rte_gpu_info {
    const char *name;
    uint64_t context;
    int16_t dev_id;
    int16_t parent;
    uint32_t processor_count;
    size_t total_memory;
    size_t page_size;
    int16_t numa_node;
};
 
enum rte_gpu_event {
    RTE_GPU_EVENT_NEW,
    RTE_GPU_EVENT_DEL,
};
 
typedef void (rte_gpu_callback_t)(int16_t dev_id,
        enum rte_gpu_event event, void *user_data);
 
enum rte_gpu_comm_flag_type {
    RTE_GPU_COMM_FLAG_CPU = 0,
};
 
struct rte_gpu_comm_flag {
    uint16_t dev_id;
    uint32_t *ptr;
    enum rte_gpu_comm_flag_type mtype;
};
 
struct rte_gpu_comm_pkt {
    uintptr_t addr;
    size_t size;
};
 
enum rte_gpu_comm_list_status {
    RTE_GPU_COMM_LIST_FREE = 0,
    RTE_GPU_COMM_LIST_READY,
    RTE_GPU_COMM_LIST_DONE,
    RTE_GPU_COMM_LIST_ERROR,
};
 
struct rte_gpu_comm_list {
    uint16_t dev_id;
    struct rte_mbuf **mbufs;
    struct rte_gpu_comm_pkt *pkt_list;
    uint32_t num_pkts;
    enum rte_gpu_comm_list_status *status_h;
    enum rte_gpu_comm_list_status *status_d;
};
 
__rte_experimental
int rte_gpu_init(size_t dev_max);
 
__rte_experimental
uint16_t rte_gpu_count_avail(void);
 
__rte_experimental
bool rte_gpu_is_valid(int16_t dev_id);
 
__rte_experimental
int16_t rte_gpu_add_child(const char *name,
        int16_t parent, uint64_t child_context);
 
__rte_experimental
int16_t rte_gpu_find_next(int16_t dev_id, int16_t parent);
 
#define RTE_GPU_FOREACH(dev_id) \
    RTE_GPU_FOREACH_CHILD(dev_id, RTE_GPU_ID_ANY)
 
#define RTE_GPU_FOREACH_PARENT(dev_id) \
    RTE_GPU_FOREACH_CHILD(dev_id, RTE_GPU_ID_NONE)
 
#define RTE_GPU_FOREACH_CHILD(dev_id, parent) \
    for (dev_id = rte_gpu_find_next(0, parent); \
         dev_id >= 0; \
         dev_id = rte_gpu_find_next(dev_id + 1, parent))
 
__rte_experimental
int rte_gpu_close(int16_t dev_id);
 
__rte_experimental
int rte_gpu_callback_register(int16_t dev_id, enum rte_gpu_event event,
        rte_gpu_callback_t *function, void *user_data);
 
__rte_experimental
int rte_gpu_callback_unregister(int16_t dev_id, enum rte_gpu_event event,
        rte_gpu_callback_t *function, void *user_data);
 
__rte_experimental
int rte_gpu_info_get(int16_t dev_id, struct rte_gpu_info *info);
 
__rte_experimental
void *rte_gpu_mem_alloc(int16_t dev_id, size_t size, unsigned int align)
__rte_alloc_size(2);
 
__rte_experimental
int rte_gpu_mem_free(int16_t dev_id, void *ptr);
 
__rte_experimental
int rte_gpu_mem_register(int16_t dev_id, size_t size, void *ptr);
 
__rte_experimental
int rte_gpu_mem_unregister(int16_t dev_id, void *ptr);
 
__rte_experimental
void *rte_gpu_mem_cpu_map(int16_t dev_id, size_t size, void *ptr);
 
__rte_experimental
int rte_gpu_mem_cpu_unmap(int16_t dev_id, void *ptr);
 
__rte_experimental
int rte_gpu_wmb(int16_t dev_id);
 
__rte_experimental
int rte_gpu_comm_create_flag(uint16_t dev_id,
        struct rte_gpu_comm_flag *devflag,
        enum rte_gpu_comm_flag_type mtype);
 
__rte_experimental
int rte_gpu_comm_destroy_flag(struct rte_gpu_comm_flag *devflag);
 
__rte_experimental
int rte_gpu_comm_set_flag(struct rte_gpu_comm_flag *devflag,
        uint32_t val);
 
__rte_experimental
int rte_gpu_comm_get_flag_value(struct rte_gpu_comm_flag *devflag,
        uint32_t *val);
 
__rte_experimental
struct rte_gpu_comm_list *rte_gpu_comm_create_list(uint16_t dev_id,
        uint32_t num_comm_items);
 
__rte_experimental
int rte_gpu_comm_destroy_list(struct rte_gpu_comm_list *comm_list,
        uint32_t num_comm_items);
 
__rte_experimental
int rte_gpu_comm_populate_list_pkts(struct rte_gpu_comm_list *comm_list_item,
        struct rte_mbuf **mbufs, uint32_t num_mbufs);
 
__rte_experimental
int rte_gpu_comm_set_status(struct rte_gpu_comm_list *comm_list_item,
        enum rte_gpu_comm_list_status status);
 
__rte_experimental
int rte_gpu_comm_get_status(struct rte_gpu_comm_list *comm_list_item,
        enum rte_gpu_comm_list_status *status);
 
__rte_experimental
int rte_gpu_comm_cleanup_list(struct rte_gpu_comm_list *comm_list_item);
 
#ifdef __cplusplus
}
#endif
 
#endif /* RTE_GPUDEV_H */