DPDK  20.11.3
rte_pci.h
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1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2015 Intel Corporation.
3  * Copyright 2013-2014 6WIND S.A.
4  */
5 
6 #ifndef _RTE_PCI_H_
7 #define _RTE_PCI_H_
8 
15 #ifdef __cplusplus
16 extern "C" {
17 #endif
18 
19 #include <stdio.h>
20 #include <limits.h>
21 #include <sys/queue.h>
22 #include <inttypes.h>
23 #include <sys/types.h>
24 
25 /*
26  * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
27  * configuration space. PCI-X Mode 2 and PCIe devices have 4096 bytes of
28  * configuration space.
29  */
30 #define RTE_PCI_CFG_SPACE_SIZE 256
31 #define RTE_PCI_CFG_SPACE_EXP_SIZE 4096
32 
33 #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
34 #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
35 
36 /* PCI Express capability registers */
37 #define RTE_PCI_EXP_DEVCTL 8 /* Device Control */
38 
39 /* Extended Capabilities (PCI-X 2.0 and Express) */
40 #define RTE_PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
41 #define RTE_PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
42 
43 #define RTE_PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
44 #define RTE_PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
45 #define RTE_PCI_EXT_CAP_ID_SRIOV 0x10 /* SR-IOV*/
46 
47 /* Single Root I/O Virtualization */
48 #define RTE_PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
49 #define RTE_PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
50 #define RTE_PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
51 #define RTE_PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
52 #define RTE_PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
53 #define RTE_PCI_SRIOV_FUNC_LINK 0x12 /* Function Dependency Link */
54 #define RTE_PCI_SRIOV_VF_OFFSET 0x14 /* First VF Offset */
55 #define RTE_PCI_SRIOV_VF_STRIDE 0x16 /* Following VF Stride */
56 #define RTE_PCI_SRIOV_VF_DID 0x1a /* VF Device ID */
57 #define RTE_PCI_SRIOV_SUP_PGSIZE 0x1c /* Supported Page Sizes */
58 
60 #define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
61 #define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")
62 
64 #define PCI_SHORT_PRI_FMT "%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
65 
67 #define PCI_FMT_NVAL 4
68 
70 #define PCI_RESOURCE_FMT_NVAL 3
71 
73 #define PCI_MAX_RESOURCE 6
74 
79 struct rte_pci_id {
80  uint32_t class_id;
81  uint16_t vendor_id;
82  uint16_t device_id;
85 };
86 
90 struct rte_pci_addr {
91  uint32_t domain;
92  uint8_t bus;
93  uint8_t devid;
94  uint8_t function;
95 };
96 
98 #define PCI_ANY_ID (0xffff)
99 #define RTE_CLASS_ANY_ID (0xffffff)
100 
113 void rte_pci_device_name(const struct rte_pci_addr *addr,
114  char *output, size_t size);
115 
128 int rte_pci_addr_cmp(const struct rte_pci_addr *addr,
129  const struct rte_pci_addr *addr2);
130 
131 
144 int rte_pci_addr_parse(const char *str, struct rte_pci_addr *addr);
145 
146 #ifdef __cplusplus
147 }
148 #endif
149 
150 #endif /* _RTE_PCI_H_ */
int rte_pci_addr_parse(const char *str, struct rte_pci_addr *addr)
uint16_t device_id
Definition: rte_pci.h:82
uint8_t bus
Definition: rte_pci.h:92
uint32_t class_id
Definition: rte_pci.h:80
uint8_t devid
Definition: rte_pci.h:93
uint16_t subsystem_device_id
Definition: rte_pci.h:84
uint32_t domain
Definition: rte_pci.h:91
void rte_pci_device_name(const struct rte_pci_addr *addr, char *output, size_t size)
uint16_t subsystem_vendor_id
Definition: rte_pci.h:83
int rte_pci_addr_cmp(const struct rte_pci_addr *addr, const struct rte_pci_addr *addr2)
uint16_t vendor_id
Definition: rte_pci.h:81