DPDK  19.11.14-rc1
rte_eth_ctrl.h
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1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2015 Intel Corporation
3  */
4 
5 #ifndef _RTE_ETH_CTRL_H_
6 #define _RTE_ETH_CTRL_H_
7 
8 #include <stdint.h>
9 #include <rte_common.h>
10 #include <rte_ether.h>
11 #include "rte_flow.h"
12 #include "rte_ethdev.h"
13 
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25 
30  RTE_ETH_FILTER_NONE = 0,
31  RTE_ETH_FILTER_MACVLAN,
32  RTE_ETH_FILTER_ETHERTYPE,
33  RTE_ETH_FILTER_FLEXIBLE,
34  RTE_ETH_FILTER_SYN,
35  RTE_ETH_FILTER_NTUPLE,
36  RTE_ETH_FILTER_TUNNEL,
37  RTE_ETH_FILTER_FDIR,
38  RTE_ETH_FILTER_HASH,
39  RTE_ETH_FILTER_L2_TUNNEL,
40  RTE_ETH_FILTER_GENERIC,
41  RTE_ETH_FILTER_MAX
42 };
43 
58  RTE_ETH_FILTER_OP_MAX
59 };
60 
70 };
71 
76  uint8_t is_vf;
77  uint16_t dst_id;
79  struct rte_ether_addr mac_addr;
80 };
81 
86 #define RTE_ETHTYPE_FLAGS_MAC 0x0001
87 #define RTE_ETHTYPE_FLAGS_DROP 0x0002
94 struct rte_eth_ethertype_filter {
95  struct rte_ether_addr mac_addr;
96  uint16_t ether_type;
97  uint16_t flags;
98  uint16_t queue;
99 };
100 
101 #define RTE_FLEX_FILTER_MAXLEN 128
102 #define RTE_FLEX_FILTER_MASK_SIZE \
103  (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
104 
112  uint16_t len;
113  uint8_t bytes[RTE_FLEX_FILTER_MAXLEN];
116  uint8_t priority;
117  uint16_t queue;
118 };
119 
126  uint8_t hig_pri;
128  uint16_t queue;
129 };
130 
135 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
136 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
137 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
138 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
139 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
140 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
142 #define RTE_5TUPLE_FLAGS ( \
143  RTE_NTUPLE_FLAGS_DST_IP | \
144  RTE_NTUPLE_FLAGS_SRC_IP | \
145  RTE_NTUPLE_FLAGS_DST_PORT | \
146  RTE_NTUPLE_FLAGS_SRC_PORT | \
147  RTE_NTUPLE_FLAGS_PROTO)
148 
149 #define RTE_2TUPLE_FLAGS ( \
150  RTE_NTUPLE_FLAGS_DST_PORT | \
151  RTE_NTUPLE_FLAGS_PROTO)
152 
153 #define RTE_NTUPLE_TCP_FLAGS_MASK 0x3F
160 struct rte_eth_ntuple_filter {
161  uint16_t flags;
162  uint32_t dst_ip;
163  uint32_t dst_ip_mask;
164  uint32_t src_ip;
165  uint32_t src_ip_mask;
166  uint16_t dst_port;
167  uint16_t dst_port_mask;
168  uint16_t src_port;
169  uint16_t src_port_mask;
170  uint8_t proto;
171  uint8_t proto_mask;
175  uint8_t tcp_flags;
176  uint16_t priority;
178  uint16_t queue;
179 };
180 
184 #define ETH_TUNNEL_FILTER_OMAC 0x01
185 #define ETH_TUNNEL_FILTER_OIP 0x02
186 #define ETH_TUNNEL_FILTER_TENID 0x04
187 #define ETH_TUNNEL_FILTER_IMAC 0x08
188 #define ETH_TUNNEL_FILTER_IVLAN 0x10
189 #define ETH_TUNNEL_FILTER_IIP 0x20
191 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
192  ETH_TUNNEL_FILTER_IVLAN)
193 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
194  ETH_TUNNEL_FILTER_IVLAN | \
195  ETH_TUNNEL_FILTER_TENID)
196 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
197  ETH_TUNNEL_FILTER_TENID)
198 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
199  ETH_TUNNEL_FILTER_TENID | \
200  ETH_TUNNEL_FILTER_IMAC)
201 
208 };
209 
214  struct rte_ether_addr outer_mac;
215  struct rte_ether_addr inner_mac;
216  uint16_t inner_vlan;
217  enum rte_tunnel_iptype ip_type;
221  union {
222  uint32_t ipv4_addr;
223  uint32_t ipv6_addr[4];
224  } ip_addr;
226  uint16_t filter_type;
227  enum rte_eth_tunnel_type tunnel_type;
228  uint32_t tenant_id;
229  uint16_t queue_id;
230 };
231 
236  RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
237  RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
238  RTE_ETH_GLOBAL_CFG_TYPE_MAX,
239 };
240 
245  enum rte_eth_global_cfg_type cfg_type;
246  union {
247  uint8_t gre_key_len;
248  uint64_t reserved;
249  } cfg;
250 };
251 
252 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
253 #define RTE_ETH_INSET_SIZE_MAX 128
258 enum rte_eth_input_set_field {
259  RTE_ETH_INPUT_SET_UNKNOWN = 0,
260 
261  /* L2 */
262  RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
263  RTE_ETH_INPUT_SET_L2_DST_MAC,
264  RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
265  RTE_ETH_INPUT_SET_L2_INNER_VLAN,
266  RTE_ETH_INPUT_SET_L2_ETHERTYPE,
267 
268  /* L3 */
269  RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
270  RTE_ETH_INPUT_SET_L3_DST_IP4,
271  RTE_ETH_INPUT_SET_L3_SRC_IP6,
272  RTE_ETH_INPUT_SET_L3_DST_IP6,
273  RTE_ETH_INPUT_SET_L3_IP4_TOS,
274  RTE_ETH_INPUT_SET_L3_IP4_PROTO,
275  RTE_ETH_INPUT_SET_L3_IP6_TC,
276  RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
277  RTE_ETH_INPUT_SET_L3_IP4_TTL,
278  RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
279 
280  /* L4 */
281  RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
282  RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
283  RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
284  RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
285  RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
286  RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
287  RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
288 
289  /* Tunnel */
290  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
291  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
292  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
293  RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
294  RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
295 
296  /* Flexible Payload */
297  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
298  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
299  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
300  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
301  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
302  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
303  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
304  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
305 
306  RTE_ETH_INPUT_SET_DEFAULT = 65533,
307  RTE_ETH_INPUT_SET_NONE = 65534,
308  RTE_ETH_INPUT_SET_MAX = 65535,
309 };
310 
315  RTE_ETH_INPUT_SET_OP_UNKNOWN,
318  RTE_ETH_INPUT_SET_OP_MAX
319 };
320 
321 
327  uint16_t flow_type;
328  uint16_t inset_size;
330  enum rte_filter_input_set_op op;
331 };
332 
337  uint16_t ether_type;
338 };
339 
344  uint32_t src_ip;
345  uint32_t dst_ip;
346  uint8_t tos;
347  uint8_t ttl;
348  uint8_t proto;
349 };
350 
355  struct rte_eth_ipv4_flow ip;
356  uint16_t src_port;
357  uint16_t dst_port;
358 };
359 
364  struct rte_eth_ipv4_flow ip;
365  uint16_t src_port;
366  uint16_t dst_port;
367 };
368 
373  struct rte_eth_ipv4_flow ip;
374  uint16_t src_port;
375  uint16_t dst_port;
376  uint32_t verify_tag;
377 };
378 
383  uint32_t src_ip[4];
384  uint32_t dst_ip[4];
385  uint8_t tc;
386  uint8_t proto;
387  uint8_t hop_limits;
388 };
389 
394  struct rte_eth_ipv6_flow ip;
395  uint16_t src_port;
396  uint16_t dst_port;
397 };
398 
403  struct rte_eth_ipv6_flow ip;
404  uint16_t src_port;
405  uint16_t dst_port;
406 };
407 
412  struct rte_eth_ipv6_flow ip;
413  uint16_t src_port;
414  uint16_t dst_port;
415  uint32_t verify_tag;
416 };
417 
422  struct rte_ether_addr mac_addr;
423 };
424 
429  RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
430  RTE_FDIR_TUNNEL_TYPE_NVGRE,
431  RTE_FDIR_TUNNEL_TYPE_VXLAN,
432 };
433 
439  enum rte_eth_fdir_tunnel_type tunnel_type;
441  uint32_t tunnel_id;
442  struct rte_ether_addr mac_addr;
443 };
444 
450  struct rte_eth_l2_flow l2_flow;
451  struct rte_eth_udpv4_flow udp4_flow;
452  struct rte_eth_tcpv4_flow tcp4_flow;
453  struct rte_eth_sctpv4_flow sctp4_flow;
454  struct rte_eth_ipv4_flow ip4_flow;
455  struct rte_eth_udpv6_flow udp6_flow;
456  struct rte_eth_tcpv6_flow tcp6_flow;
457  struct rte_eth_sctpv6_flow sctp6_flow;
458  struct rte_eth_ipv6_flow ipv6_flow;
459  struct rte_eth_mac_vlan_flow mac_vlan_flow;
460  struct rte_eth_tunnel_flow tunnel_flow;
461 };
462 
467  uint16_t vlan_tci;
468  uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
470  uint8_t is_vf;
471  uint16_t dst_id;
472 };
473 
478  uint16_t flow_type;
479  union rte_eth_fdir_flow flow;
481  struct rte_eth_fdir_flow_ext flow_ext;
483 };
484 
489  RTE_ETH_FDIR_ACCEPT = 0,
490  RTE_ETH_FDIR_REJECT,
491  RTE_ETH_FDIR_PASSTHRU,
492 };
493 
503 };
504 
509  uint16_t rx_queue;
510  enum rte_eth_fdir_behavior behavior;
511  enum rte_eth_fdir_status report_status;
512  uint8_t flex_off;
516 };
517 
524  uint32_t soft_id;
526  struct rte_eth_fdir_input input;
527  struct rte_eth_fdir_action action;
528 };
529 
535  uint16_t vlan_tci_mask;
537  struct rte_eth_ipv4_flow ipv4_mask;
539  struct rte_eth_ipv6_flow ipv6_mask;
541  uint16_t src_port_mask;
543  uint16_t dst_port_mask;
548  uint32_t tunnel_id_mask;
551 };
552 
557  RTE_ETH_PAYLOAD_UNKNOWN = 0,
558  RTE_ETH_RAW_PAYLOAD,
559  RTE_ETH_L2_PAYLOAD,
560  RTE_ETH_L3_PAYLOAD,
561  RTE_ETH_L4_PAYLOAD,
562  RTE_ETH_PAYLOAD_MAX = 8,
563 };
564 
571  uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN];
576 };
577 
583  uint16_t flow_type;
586 };
587 
593  uint16_t nb_payloads;
594  uint16_t nb_flexmasks;
595  struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
597  struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
599 };
600 
610 };
611 
612 #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
613 #define RTE_FLOW_MASK_ARRAY_SIZE \
614  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
615 
624  enum rte_fdir_mode mode;
625  struct rte_eth_fdir_masks mask;
627  struct rte_eth_fdir_flex_conf flex_conf;
628  uint32_t guarant_spc;
629  uint32_t best_spc;
631  uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
632  uint32_t max_flexpayload;
648 };
649 
655  uint32_t collision;
656  uint32_t free;
657  uint32_t maxhash;
660  uint32_t maxlen;
661  uint64_t add;
662  uint64_t remove;
663  uint64_t f_add;
664  uint64_t f_remove;
665  uint32_t guarant_cnt;
666  uint32_t best_cnt;
667 };
668 
673  RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
676  RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
677 };
678 
686  union {
688  struct rte_eth_input_set_conf input_set_conf;
689  } info;
690 };
691 
703  RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
710  RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
711 };
712 
713 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \
714  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
715 
725  enum rte_eth_hash_function hash_func;
727  uint64_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
729  uint64_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
730 };
731 
739  union {
741  uint8_t enable;
743  struct rte_eth_hash_global_conf global_conf;
745  struct rte_eth_input_set_conf input_set_conf;
746  } info;
747 };
748 
753  enum rte_eth_tunnel_type l2_tunnel_type;
754  uint16_t ether_type; /* ether type in l2 header */
755  uint32_t tunnel_id; /* port tag id for e-tag */
756  uint16_t vf_id; /* VF id for tag insertion */
757  uint32_t pool; /* destination pool for tag based forwarding */
758 };
759 
760 #ifdef __cplusplus
761 }
762 #endif
763 
764 #endif /* _RTE_ETH_CTRL_H_ */
#define RTE_ETH_FDIR_MAX_FLEXLEN
Definition: rte_eth_ctrl.h:252
rte_eth_input_set_field
Definition: rte_eth_ctrl.h:258
uint32_t flex_payload_unit
Definition: rte_eth_ctrl.h:635
rte_eth_fdir_filter_info_type
Definition: rte_eth_ctrl.h:672
#define RTE_FLEX_FILTER_MAXLEN
Definition: rte_eth_ctrl.h:101
rte_filter_op
Definition: rte_eth_ctrl.h:47
uint16_t src_port_mask
Definition: rte_eth_ctrl.h:541
rte_filter_input_set_op
Definition: rte_eth_ctrl.h:314
uint32_t guarant_spc
Definition: rte_eth_ctrl.h:628
uint32_t max_flex_payload_segment_num
Definition: rte_eth_ctrl.h:638
rte_eth_fdir_status
Definition: rte_eth_ctrl.h:498
uint32_t max_flex_bitmask_num
Definition: rte_eth_ctrl.h:647
uint32_t flex_bitmask_unit
Definition: rte_eth_ctrl.h:645
rte_eth_payload_type
Definition: rte_eth_ctrl.h:556
enum rte_mac_filter_type filter_type
Definition: rte_eth_ctrl.h:78
rte_eth_hash_function
Definition: rte_flow.h:2097
uint16_t dst_port_mask
Definition: rte_eth_ctrl.h:543
uint16_t vlan_tci_mask
Definition: rte_eth_ctrl.h:535
rte_eth_global_cfg_type
Definition: rte_eth_ctrl.h:235
uint8_t tunnel_type_mask
Definition: rte_eth_ctrl.h:549
uint32_t tunnel_id_mask
Definition: rte_eth_ctrl.h:548
uint16_t flex_payload_limit
Definition: rte_eth_ctrl.h:642
rte_filter_type
Definition: rte_eth_ctrl.h:29
rte_tunnel_iptype
Definition: rte_eth_ctrl.h:205
#define RTE_ETH_INSET_SIZE_MAX
Definition: rte_eth_ctrl.h:253
uint8_t mac_addr_byte_mask
Definition: rte_eth_ctrl.h:546
rte_eth_fdir_tunnel_type
Definition: rte_eth_ctrl.h:428
rte_mac_filter_type
Definition: rte_eth_ctrl.h:64
rte_eth_tunnel_type
Definition: rte_ethdev.h:965
uint32_t max_flexpayload
Definition: rte_eth_ctrl.h:632
rte_eth_fdir_behavior
Definition: rte_eth_ctrl.h:488
rte_fdir_mode
Definition: rte_eth_ctrl.h:604
uint16_t ether_type
Definition: rte_eth_ctrl.h:337
#define RTE_FLEX_FILTER_MASK_SIZE
Definition: rte_eth_ctrl.h:102
rte_eth_hash_filter_info_type
Definition: rte_eth_ctrl.h:702