34 #ifndef _RTE_ETH_CTRL_H_
35 #define _RTE_ETH_CTRL_H_
63 #define RTE_ETH_FLOW_UNKNOWN 0
64 #define RTE_ETH_FLOW_RAW 1
65 #define RTE_ETH_FLOW_IPV4 2
66 #define RTE_ETH_FLOW_FRAG_IPV4 3
67 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4
68 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5
69 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6
70 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7
71 #define RTE_ETH_FLOW_IPV6 8
72 #define RTE_ETH_FLOW_FRAG_IPV6 9
73 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10
74 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11
75 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12
76 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13
77 #define RTE_ETH_FLOW_L2_PAYLOAD 14
78 #define RTE_ETH_FLOW_IPV6_EX 15
79 #define RTE_ETH_FLOW_IPV6_TCP_EX 16
80 #define RTE_ETH_FLOW_IPV6_UDP_EX 17
81 #define RTE_ETH_FLOW_PORT 18
83 #define RTE_ETH_FLOW_VXLAN 19
84 #define RTE_ETH_FLOW_GENEVE 20
85 #define RTE_ETH_FLOW_NVGRE 21
86 #define RTE_ETH_FLOW_MAX 22
92 RTE_ETH_FILTER_NONE = 0,
93 RTE_ETH_FILTER_MACVLAN,
94 RTE_ETH_FILTER_ETHERTYPE,
95 RTE_ETH_FILTER_FLEXIBLE,
97 RTE_ETH_FILTER_NTUPLE,
98 RTE_ETH_FILTER_TUNNEL,
101 RTE_ETH_FILTER_L2_TUNNEL,
102 RTE_ETH_FILTER_GENERIC,
120 RTE_ETH_FILTER_OP_MAX
148 #define RTE_ETHTYPE_FLAGS_MAC 0x0001
149 #define RTE_ETHTYPE_FLAGS_DROP 0x0002
156 struct rte_eth_ethertype_filter {
163 #define RTE_FLEX_FILTER_MAXLEN 128
164 #define RTE_FLEX_FILTER_MASK_SIZE \
165 (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
197 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
198 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
199 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
200 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
201 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
202 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
204 #define RTE_5TUPLE_FLAGS ( \
205 RTE_NTUPLE_FLAGS_DST_IP | \
206 RTE_NTUPLE_FLAGS_SRC_IP | \
207 RTE_NTUPLE_FLAGS_DST_PORT | \
208 RTE_NTUPLE_FLAGS_SRC_PORT | \
209 RTE_NTUPLE_FLAGS_PROTO)
211 #define RTE_2TUPLE_FLAGS ( \
212 RTE_NTUPLE_FLAGS_DST_PORT | \
213 RTE_NTUPLE_FLAGS_PROTO)
215 #define TCP_URG_FLAG 0x20
216 #define TCP_ACK_FLAG 0x10
217 #define TCP_PSH_FLAG 0x08
218 #define TCP_RST_FLAG 0x04
219 #define TCP_SYN_FLAG 0x02
220 #define TCP_FIN_FLAG 0x01
221 #define TCP_FLAG_ALL 0x3F
253 RTE_TUNNEL_TYPE_NONE = 0,
254 RTE_TUNNEL_TYPE_VXLAN,
255 RTE_TUNNEL_TYPE_GENEVE,
256 RTE_TUNNEL_TYPE_TEREDO,
257 RTE_TUNNEL_TYPE_NVGRE,
258 RTE_TUNNEL_TYPE_IP_IN_GRE,
259 RTE_L2_TUNNEL_TYPE_E_TAG,
266 #define ETH_TUNNEL_FILTER_OMAC 0x01
267 #define ETH_TUNNEL_FILTER_OIP 0x02
268 #define ETH_TUNNEL_FILTER_TENID 0x04
269 #define ETH_TUNNEL_FILTER_IMAC 0x08
270 #define ETH_TUNNEL_FILTER_IVLAN 0x10
271 #define ETH_TUNNEL_FILTER_IIP 0x20
273 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
274 ETH_TUNNEL_FILTER_IVLAN)
275 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
276 ETH_TUNNEL_FILTER_IVLAN | \
277 ETH_TUNNEL_FILTER_TENID)
278 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
279 ETH_TUNNEL_FILTER_TENID)
280 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
281 ETH_TUNNEL_FILTER_TENID | \
282 ETH_TUNNEL_FILTER_IMAC)
318 RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
319 RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
320 RTE_ETH_GLOBAL_CFG_TYPE_MAX,
334 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
335 #define RTE_ETH_INSET_SIZE_MAX 128
340 enum rte_eth_input_set_field {
341 RTE_ETH_INPUT_SET_UNKNOWN = 0,
344 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
345 RTE_ETH_INPUT_SET_L2_DST_MAC,
346 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
347 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
348 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
351 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
352 RTE_ETH_INPUT_SET_L3_DST_IP4,
353 RTE_ETH_INPUT_SET_L3_SRC_IP6,
354 RTE_ETH_INPUT_SET_L3_DST_IP6,
355 RTE_ETH_INPUT_SET_L3_IP4_TOS,
356 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
357 RTE_ETH_INPUT_SET_L3_IP6_TC,
358 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
359 RTE_ETH_INPUT_SET_L3_IP4_TTL,
360 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
363 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
364 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
365 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
366 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
367 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
368 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
369 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
372 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
373 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
374 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
375 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
376 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
379 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
380 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
381 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
382 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
383 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
384 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
385 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
386 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
388 RTE_ETH_INPUT_SET_DEFAULT = 65533,
389 RTE_ETH_INPUT_SET_NONE = 65534,
390 RTE_ETH_INPUT_SET_MAX = 65535,
397 RTE_ETH_INPUT_SET_OP_UNKNOWN,
400 RTE_ETH_INPUT_SET_OP_MAX
511 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
512 RTE_FDIR_TUNNEL_TYPE_NVGRE,
513 RTE_FDIR_TUNNEL_TYPE_VXLAN,
571 RTE_ETH_FDIR_ACCEPT = 0,
573 RTE_ETH_FDIR_PASSTHRU,
639 RTE_ETH_PAYLOAD_UNKNOWN = 0,
644 RTE_ETH_PAYLOAD_MAX = 8,
694 #define UINT32_BIT (CHAR_BIT * sizeof(uint32_t))
695 #define RTE_FLOW_MASK_ARRAY_SIZE \
696 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)
755 RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
758 RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
785 RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
792 RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
799 RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
802 RTE_ETH_HASH_FUNCTION_MAX,
805 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \
806 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)
#define RTE_ETH_FDIR_MAX_FLEXLEN
enum rte_eth_fdir_status report_status
uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN]
uint32_t flex_payload_unit
struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX]
struct rte_eth_ipv4_flow ip
rte_eth_fdir_filter_info_type
union rte_eth_tunnel_filter_conf::@59 ip_addr
#define RTE_FLEX_FILTER_MAXLEN
struct rte_eth_hash_global_conf global_conf
enum rte_eth_hash_function hash_func
struct rte_eth_fdir_action action
struct rte_eth_input_set_conf input_set_conf
uint32_t max_flex_payload_segment_num
struct ether_addr inner_mac
struct rte_eth_ipv6_flow ipv6_mask
struct rte_eth_fdir_input input
struct rte_eth_ipv4_flow ipv4_mask
struct rte_eth_ipv4_flow ip
uint32_t max_flex_bitmask_num
struct rte_eth_ipv4_flow ip
uint32_t flex_bitmask_unit
uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN]
struct rte_eth_fdir_flex_conf flex_conf
enum rte_mac_filter_type filter_type
enum rte_eth_fdir_tunnel_type tunnel_type
uint32_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE]
union rte_eth_hash_filter_info::@62 info
enum rte_eth_fdir_filter_info_type info_type
struct rte_eth_ipv6_flow ip
enum rte_eth_tunnel_type tunnel_type
uint16_t flex_payload_limit
#define RTE_ETH_INSET_SIZE_MAX
struct rte_eth_input_set_conf input_set_conf
uint8_t mac_addr_byte_mask
struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX]
uint32_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE]
enum rte_eth_global_cfg_type cfg_type
enum rte_eth_payload_type type
enum rte_eth_hash_filter_info_type info_type
union rte_eth_fdir_filter_info::@61 info
#define RTE_FLEX_FILTER_MASK_SIZE
uint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE]
enum rte_eth_fdir_behavior behavior
uint8_t bytes[RTE_FLEX_FILTER_MAXLEN]
uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]
enum rte_tunnel_iptype ip_type
struct rte_eth_ipv6_flow ip
struct ether_addr outer_mac
struct ether_addr mac_addr
uint8_t mask[RTE_FLEX_FILTER_MASK_SIZE]
struct rte_eth_ipv6_flow ip
rte_eth_hash_filter_info_type
struct ether_addr mac_addr