rte_prefetch.h

Go to the documentation of this file.

/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2010-2015 Intel Corporation
 */
 
#ifndef _RTE_PREFETCH_H_
#define _RTE_PREFETCH_H_
 
#include <rte_compat.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
static inline void rte_prefetch0(const volatile void *p);
 
static inline void rte_prefetch1(const volatile void *p);
 
static inline void rte_prefetch2(const volatile void *p);
 
static inline void rte_prefetch_non_temporal(const volatile void *p);
 
__rte_experimental
static inline void
rte_prefetch0_write(const void *p)
{
    /* 1 indicates intention to write, 3 sets target cache level to L1. See
     * GCC docs where these integer constants are described in more detail:
     *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
     */
#ifdef RTE_TOOLCHAIN_MSVC
    rte_prefetch0(p);
#else
    __builtin_prefetch(p, 1, 3);
#endif
}
 
__rte_experimental
static inline void
rte_prefetch1_write(const void *p)
{
    /* 1 indicates intention to write, 2 sets target cache level to L2. See
     * GCC docs where these integer constants are described in more detail:
     *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
     */
#ifdef RTE_TOOLCHAIN_MSVC
    rte_prefetch1(p);
#else
    __builtin_prefetch(p, 1, 2);
#endif
}
 
__rte_experimental
static inline void
rte_prefetch2_write(const void *p)
{
    /* 1 indicates intention to write, 1 sets target cache level to L3. See
     * GCC docs where these integer constants are described in more detail:
     *  https://gcc.gnu.org/onlinedocs/gcc/Other-Builtins.html
     */
#ifdef RTE_TOOLCHAIN_MSVC
    rte_prefetch2(p);
#else
    __builtin_prefetch(p, 1, 1);
#endif
}
 
__rte_experimental
static inline void
rte_cldemote(const volatile void *p);
 
#ifdef __cplusplus
}
#endif
 
#endif /* _RTE_PREFETCH_H_ */