rte_pmd_mlx5.h

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/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright 2020 Mellanox Technologies, Ltd
 */
 
#ifndef RTE_PMD_PRIVATE_MLX5_H_
#define RTE_PMD_PRIVATE_MLX5_H_
 
#include <stdint.h>
 
#include <rte_byteorder.h>
#include <rte_compat.h>
#include <rte_per_lcore.h>
 
#ifdef __cplusplus
extern "C" {
#endif
 
#define RTE_PMD_MLX5_FINE_GRANULARITY_INLINE "mlx5_fine_granularity_inline"
 
__rte_experimental
int rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n);
 
#define RTE_PMD_MLX5_DOMAIN_BIT_NIC_RX  (1 << 0) 
#define RTE_PMD_MLX5_DOMAIN_BIT_NIC_TX  (1 << 1) 
#define RTE_PMD_MLX5_DOMAIN_BIT_FDB (1 << 2) 
__rte_experimental
int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains);
 
#define RTE_PMD_MLX5_EXTERNAL_RX_QUEUE_ID_MIN (UINT16_MAX - 1000 + 1)
 
#define MLX5_EXTERNAL_TX_QUEUE_ID_MIN (UINT16_MAX - 1000 + 1)
 
#define RTE_PMD_MLX5_LINEAR_HASH_TAG_INDEX 255
 
__rte_experimental
int rte_pmd_mlx5_external_rx_queue_id_map(uint16_t port_id, uint16_t dpdk_idx,
                      uint32_t hw_idx);
 
__rte_experimental
int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id,
                        uint16_t dpdk_idx);
 
__rte_experimental
int rte_pmd_mlx5_external_tx_queue_id_map(uint16_t port_id, uint16_t dpdk_idx,
                      uint32_t hw_idx);
 
__rte_experimental
int rte_pmd_mlx5_external_tx_queue_id_unmap(uint16_t port_id,
                        uint16_t dpdk_idx);
 
#define RTE_PMD_MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED 0
 
__rte_experimental
int rte_pmd_mlx5_host_shaper_config(int port_id, uint8_t rate, uint32_t flags);
 
__rte_experimental
int rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num);
 
/* MLX5 flow engine mode definition for live migration. */
enum rte_pmd_mlx5_flow_engine_mode {
    RTE_PMD_MLX5_FLOW_ENGINE_MODE_ACTIVE, /* active means high priority, effective in HW. */
    RTE_PMD_MLX5_FLOW_ENGINE_MODE_STANDBY, /* standby mode with lower priority flow rules. */
};
 
#define RTE_PMD_MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS      RTE_BIT32(0)
 
__rte_experimental
int rte_pmd_mlx5_flow_engine_set_mode(enum rte_pmd_mlx5_flow_engine_mode mode, uint32_t flags);
 
struct rte_pmd_mlx5_geneve_tlv {
    rte_be16_t option_class;
    uint8_t option_type;
    uint8_t option_len;
    uint8_t match_on_class_mode;
    uint8_t offset;
    uint8_t sample_len;
    rte_be32_t *match_data_mask;
};
 
__rte_experimental
void *
rte_pmd_mlx5_create_geneve_tlv_parser(uint16_t port_id,
                      const struct rte_pmd_mlx5_geneve_tlv tlv_list[],
                      uint8_t nb_options);
 
__rte_experimental
int
rte_pmd_mlx5_destroy_geneve_tlv_parser(void *handle);
 
__rte_experimental
int
rte_pmd_mlx5_rxq_dump_contexts(uint16_t port_id, uint16_t queue_id, const char *filename);
 
__rte_experimental
int
rte_pmd_mlx5_txq_dump_contexts(uint16_t port_id, uint16_t queue_id, const char *filename);
 
enum rte_pmd_mlx5_driver_event_cb_type {
    RTE_PMD_MLX5_DRIVER_EVENT_CB_TYPE_RXQ_CREATE,
    RTE_PMD_MLX5_DRIVER_EVENT_CB_TYPE_RXQ_DESTROY,
    RTE_PMD_MLX5_DRIVER_EVENT_CB_TYPE_TXQ_CREATE,
    RTE_PMD_MLX5_DRIVER_EVENT_CB_TYPE_TXQ_DESTROY,
};
 
struct rte_pmd_mlx5_driver_event_cb_queue_info {
    uint16_t dpdk_queue_id;
    uint32_t hw_queue_id;
    const char *queue_info;
};
 
struct rte_pmd_mlx5_driver_event_cb_info {
    enum rte_pmd_mlx5_driver_event_cb_type event;
    union {
        struct rte_pmd_mlx5_driver_event_cb_queue_info queue;
    };
};
 
typedef void (*rte_pmd_mlx5_driver_event_callback_t)(uint16_t port_id,
        const struct rte_pmd_mlx5_driver_event_cb_info *info,
        const void *opaque);
 
 
__rte_experimental
int
rte_pmd_mlx5_driver_event_cb_register(rte_pmd_mlx5_driver_event_callback_t cb, void *opaque);
 
__rte_experimental
int
rte_pmd_mlx5_driver_event_cb_unregister(rte_pmd_mlx5_driver_event_callback_t cb);
 
__rte_experimental
void
rte_pmd_mlx5_disable_steering(void);
 
__rte_experimental
int
rte_pmd_mlx5_enable_steering(void);
 
#ifdef __cplusplus
}
#endif
 
#endif /* RTE_PMD_PRIVATE_MLX5_H_ */