DPDK  19.08.0-rc2
 All Data Structures Files Functions Variables Typedefs Enumerations Enumerator Macros Pages
rte_eth_ctrl.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2015 Intel Corporation
3  */
4 
5 #ifndef _RTE_ETH_CTRL_H_
6 #define _RTE_ETH_CTRL_H_
7 
8 #include <stdint.h>
9 #include <rte_common.h>
10 #include "rte_ether.h"
11 #include "rte_flow.h"
12 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
29  RTE_ETH_FILTER_NONE = 0,
30  RTE_ETH_FILTER_MACVLAN,
31  RTE_ETH_FILTER_ETHERTYPE,
32  RTE_ETH_FILTER_FLEXIBLE,
33  RTE_ETH_FILTER_SYN,
34  RTE_ETH_FILTER_NTUPLE,
35  RTE_ETH_FILTER_TUNNEL,
36  RTE_ETH_FILTER_FDIR,
37  RTE_ETH_FILTER_HASH,
38  RTE_ETH_FILTER_L2_TUNNEL,
39  RTE_ETH_FILTER_GENERIC,
40  RTE_ETH_FILTER_MAX
41 };
42 
57  RTE_ETH_FILTER_OP_MAX
58 };
59 
69 };
70 
75  uint8_t is_vf;
76  uint16_t dst_id;
78  struct rte_ether_addr mac_addr;
79 };
80 
85 #define RTE_ETHTYPE_FLAGS_MAC 0x0001
86 #define RTE_ETHTYPE_FLAGS_DROP 0x0002
93 struct rte_eth_ethertype_filter {
94  struct rte_ether_addr mac_addr;
95  uint16_t ether_type;
96  uint16_t flags;
97  uint16_t queue;
98 };
99 
100 #define RTE_FLEX_FILTER_MAXLEN 128
101 #define RTE_FLEX_FILTER_MASK_SIZE \
102  (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
103 
111  uint16_t len;
115  uint8_t priority;
116  uint16_t queue;
117 };
118 
125  uint8_t hig_pri;
127  uint16_t queue;
128 };
129 
134 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
135 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
136 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
137 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
138 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
139 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
141 #define RTE_5TUPLE_FLAGS ( \
142  RTE_NTUPLE_FLAGS_DST_IP | \
143  RTE_NTUPLE_FLAGS_SRC_IP | \
144  RTE_NTUPLE_FLAGS_DST_PORT | \
145  RTE_NTUPLE_FLAGS_SRC_PORT | \
146  RTE_NTUPLE_FLAGS_PROTO)
147 
148 #define RTE_2TUPLE_FLAGS ( \
149  RTE_NTUPLE_FLAGS_DST_PORT | \
150  RTE_NTUPLE_FLAGS_PROTO)
151 
152 #define RTE_NTUPLE_TCP_FLAGS_MASK 0x3F
159 struct rte_eth_ntuple_filter {
160  uint16_t flags;
161  uint32_t dst_ip;
162  uint32_t dst_ip_mask;
163  uint32_t src_ip;
164  uint32_t src_ip_mask;
165  uint16_t dst_port;
166  uint16_t dst_port_mask;
167  uint16_t src_port;
168  uint16_t src_port_mask;
169  uint8_t proto;
170  uint8_t proto_mask;
174  uint8_t tcp_flags;
175  uint16_t priority;
177  uint16_t queue;
178 };
179 
183 #define ETH_TUNNEL_FILTER_OMAC 0x01
184 #define ETH_TUNNEL_FILTER_OIP 0x02
185 #define ETH_TUNNEL_FILTER_TENID 0x04
186 #define ETH_TUNNEL_FILTER_IMAC 0x08
187 #define ETH_TUNNEL_FILTER_IVLAN 0x10
188 #define ETH_TUNNEL_FILTER_IIP 0x20
190 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
191  ETH_TUNNEL_FILTER_IVLAN)
192 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
193  ETH_TUNNEL_FILTER_IVLAN | \
194  ETH_TUNNEL_FILTER_TENID)
195 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
196  ETH_TUNNEL_FILTER_TENID)
197 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
198  ETH_TUNNEL_FILTER_TENID | \
199  ETH_TUNNEL_FILTER_IMAC)
200 
207 };
208 
215  uint16_t inner_vlan;
220  union {
221  uint32_t ipv4_addr;
222  uint32_t ipv6_addr[4];
223  } ip_addr;
225  uint16_t filter_type;
227  uint32_t tenant_id;
228  uint16_t queue_id;
229 };
230 
235  RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
236  RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
237  RTE_ETH_GLOBAL_CFG_TYPE_MAX,
238 };
239 
245  union {
246  uint8_t gre_key_len;
247  uint64_t reserved;
248  } cfg;
249 };
250 
251 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
252 #define RTE_ETH_INSET_SIZE_MAX 128
257 enum rte_eth_input_set_field {
258  RTE_ETH_INPUT_SET_UNKNOWN = 0,
259 
260  /* L2 */
261  RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
262  RTE_ETH_INPUT_SET_L2_DST_MAC,
263  RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
264  RTE_ETH_INPUT_SET_L2_INNER_VLAN,
265  RTE_ETH_INPUT_SET_L2_ETHERTYPE,
266 
267  /* L3 */
268  RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
269  RTE_ETH_INPUT_SET_L3_DST_IP4,
270  RTE_ETH_INPUT_SET_L3_SRC_IP6,
271  RTE_ETH_INPUT_SET_L3_DST_IP6,
272  RTE_ETH_INPUT_SET_L3_IP4_TOS,
273  RTE_ETH_INPUT_SET_L3_IP4_PROTO,
274  RTE_ETH_INPUT_SET_L3_IP6_TC,
275  RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
276  RTE_ETH_INPUT_SET_L3_IP4_TTL,
277  RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
278 
279  /* L4 */
280  RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
281  RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
282  RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
283  RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
284  RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
285  RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
286  RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
287 
288  /* Tunnel */
289  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
290  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
291  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
292  RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
293  RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
294 
295  /* Flexible Payload */
296  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
297  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
298  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
299  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
300  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
301  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
302  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
303  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
304 
305  RTE_ETH_INPUT_SET_DEFAULT = 65533,
306  RTE_ETH_INPUT_SET_NONE = 65534,
307  RTE_ETH_INPUT_SET_MAX = 65535,
308 };
309 
314  RTE_ETH_INPUT_SET_OP_UNKNOWN,
317  RTE_ETH_INPUT_SET_OP_MAX
318 };
319 
320 
326  uint16_t flow_type;
327  uint16_t inset_size;
329  enum rte_filter_input_set_op op;
330 };
331 
336  uint16_t ether_type;
337 };
338 
343  uint32_t src_ip;
344  uint32_t dst_ip;
345  uint8_t tos;
346  uint8_t ttl;
347  uint8_t proto;
348 };
349 
355  uint16_t src_port;
356  uint16_t dst_port;
357 };
358 
364  uint16_t src_port;
365  uint16_t dst_port;
366 };
367 
373  uint16_t src_port;
374  uint16_t dst_port;
375  uint32_t verify_tag;
376 };
377 
382  uint32_t src_ip[4];
383  uint32_t dst_ip[4];
384  uint8_t tc;
385  uint8_t proto;
386  uint8_t hop_limits;
387 };
388 
394  uint16_t src_port;
395  uint16_t dst_port;
396 };
397 
403  uint16_t src_port;
404  uint16_t dst_port;
405 };
406 
412  uint16_t src_port;
413  uint16_t dst_port;
414  uint32_t verify_tag;
415 };
416 
422 };
423 
428  RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
429  RTE_FDIR_TUNNEL_TYPE_NVGRE,
430  RTE_FDIR_TUNNEL_TYPE_VXLAN,
431 };
432 
440  uint32_t tunnel_id;
442 };
443 
449  struct rte_eth_l2_flow l2_flow;
450  struct rte_eth_udpv4_flow udp4_flow;
451  struct rte_eth_tcpv4_flow tcp4_flow;
452  struct rte_eth_sctpv4_flow sctp4_flow;
453  struct rte_eth_ipv4_flow ip4_flow;
454  struct rte_eth_udpv6_flow udp6_flow;
455  struct rte_eth_tcpv6_flow tcp6_flow;
456  struct rte_eth_sctpv6_flow sctp6_flow;
457  struct rte_eth_ipv6_flow ipv6_flow;
458  struct rte_eth_mac_vlan_flow mac_vlan_flow;
459  struct rte_eth_tunnel_flow tunnel_flow;
460 };
461 
466  uint16_t vlan_tci;
469  uint8_t is_vf;
470  uint16_t dst_id;
471 };
472 
477  uint16_t flow_type;
482 };
483 
488  RTE_ETH_FDIR_ACCEPT = 0,
489  RTE_ETH_FDIR_REJECT,
490  RTE_ETH_FDIR_PASSTHRU,
491 };
492 
502 };
503 
508  uint16_t rx_queue;
511  uint8_t flex_off;
515 };
516 
523  uint32_t soft_id;
527 };
528 
534  uint16_t vlan_tci_mask;
540  uint16_t src_port_mask;
542  uint16_t dst_port_mask;
547  uint32_t tunnel_id_mask;
550 };
551 
556  RTE_ETH_PAYLOAD_UNKNOWN = 0,
557  RTE_ETH_RAW_PAYLOAD,
558  RTE_ETH_L2_PAYLOAD,
559  RTE_ETH_L3_PAYLOAD,
560  RTE_ETH_L4_PAYLOAD,
561  RTE_ETH_PAYLOAD_MAX = 8,
562 };
563 
575 };
576 
582  uint16_t flow_type;
585 };
586 
592  uint16_t nb_payloads;
593  uint16_t nb_flexmasks;
594  struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
596  struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
598 };
599 
609 };
610 
611 #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
612 #define RTE_FLOW_MASK_ARRAY_SIZE \
613  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
614 
624  struct rte_eth_fdir_masks mask;
627  uint32_t guarant_spc;
628  uint32_t best_spc;
630  uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
631  uint32_t max_flexpayload;
647 };
648 
654  uint32_t collision;
655  uint32_t free;
656  uint32_t maxhash;
659  uint32_t maxlen;
660  uint64_t add;
661  uint64_t remove;
662  uint64_t f_add;
663  uint64_t f_remove;
664  uint32_t guarant_cnt;
665  uint32_t best_cnt;
666 };
667 
672  RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
675  RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
676 };
677 
685  union {
688  } info;
689 };
690 
702  RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
709  RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
710 };
711 
712 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \
713  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
714 
726  uint64_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
728  uint64_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
729 };
730 
738  union {
740  uint8_t enable;
745  } info;
746 };
747 
752  enum rte_eth_tunnel_type l2_tunnel_type;
753  uint16_t ether_type; /* ether type in l2 header */
754  uint32_t tunnel_id; /* port tag id for e-tag */
755  uint16_t vf_id; /* VF id for tag insertion */
756  uint32_t pool; /* destination pool for tag based forwarding */
757 };
758 
759 #ifdef __cplusplus
760 }
761 #endif
762 
763 #endif /* _RTE_ETH_CTRL_H_ */