rte_pci.h

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/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2010-2015 Intel Corporation.
 * Copyright 2013-2014 6WIND S.A.
 */

#ifndef _RTE_PCI_H_
#define _RTE_PCI_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <stdio.h>
#include <inttypes.h>
#include <sys/types.h>

/*
 * Conventional PCI and PCI-X Mode 1 devices have 256 bytes of
 * configuration space.  PCI-X Mode 2 and PCIe devices have 4096 bytes of
 * configuration space.
 */
#define RTE_PCI_CFG_SPACE_SIZE      256
#define RTE_PCI_CFG_SPACE_EXP_SIZE  4096

#define RTE_PCI_VENDOR_ID   0x00    /* 16 bits */
#define RTE_PCI_DEVICE_ID   0x02    /* 16 bits */
#define RTE_PCI_COMMAND     0x04    /* 16 bits */

/* PCI Command Register */
#define RTE_PCI_COMMAND_MASTER  0x4 /* Bus Master Enable */

/* PCI Express capability registers */
#define RTE_PCI_EXP_DEVCTL  8   /* Device Control */

/* Extended Capabilities (PCI-X 2.0 and Express) */
#define RTE_PCI_EXT_CAP_ID(header)  (header & 0x0000ffff)
#define RTE_PCI_EXT_CAP_NEXT(header)    ((header >> 20) & 0xffc)

#define RTE_PCI_EXT_CAP_ID_ERR      0x01    /* Advanced Error Reporting */
#define RTE_PCI_EXT_CAP_ID_DSN      0x03    /* Device Serial Number */
#define RTE_PCI_EXT_CAP_ID_SRIOV    0x10    /* SR-IOV*/
#define RTE_PCI_EXT_CAP_ID_PASID    0x1B    /* Process Address Space ID */

/* Single Root I/O Virtualization */
#define RTE_PCI_SRIOV_CAP       0x04    /* SR-IOV Capabilities */
#define RTE_PCI_SRIOV_CTRL      0x08    /* SR-IOV Control */
#define RTE_PCI_SRIOV_INITIAL_VF    0x0c    /* Initial VFs */
#define RTE_PCI_SRIOV_TOTAL_VF      0x0e    /* Total VFs */
#define RTE_PCI_SRIOV_NUM_VF        0x10    /* Number of VFs */
#define RTE_PCI_SRIOV_FUNC_LINK     0x12    /* Function Dependency Link */
#define RTE_PCI_SRIOV_VF_OFFSET     0x14    /* First VF Offset */
#define RTE_PCI_SRIOV_VF_STRIDE     0x16    /* Following VF Stride */
#define RTE_PCI_SRIOV_VF_DID        0x1a    /* VF Device ID */
#define RTE_PCI_SRIOV_SUP_PGSIZE    0x1c    /* Supported Page Sizes */


/* Process Address Space ID (RTE_PCI_EXT_CAP_ID_PASID) */
#define RTE_PCI_PASID_CTRL      0x06    /* PASID control register */

#define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
#define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")

#define PCI_SHORT_PRI_FMT "%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8

#define PCI_FMT_NVAL 4

#define PCI_RESOURCE_FMT_NVAL 3

#define PCI_MAX_RESOURCE 6

struct rte_pci_id {
    uint32_t class_id;            
    uint16_t vendor_id;           
    uint16_t device_id;           
    uint16_t subsystem_vendor_id; 
    uint16_t subsystem_device_id; 
};

struct rte_pci_addr {
    uint32_t domain;                
    uint8_t bus;                    
    uint8_t devid;                  
    uint8_t function;               
};

#define RTE_PCI_ANY_ID (0xffff)

#define PCI_ANY_ID RTE_DEPRECATED(PCI_ANY_ID) RTE_PCI_ANY_ID
#define RTE_CLASS_ANY_ID (0xffffff)

void rte_pci_device_name(const struct rte_pci_addr *addr,
             char *output, size_t size);

int rte_pci_addr_cmp(const struct rte_pci_addr *addr,
             const struct rte_pci_addr *addr2);


int rte_pci_addr_parse(const char *str, struct rte_pci_addr *addr);

#ifdef __cplusplus
}
#endif

#endif /* _RTE_PCI_H_ */