rte_pci.h

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/* SPDX-License-Identifier: BSD-3-Clause
 * Copyright(c) 2010-2015 Intel Corporation.
 * Copyright 2013-2014 6WIND S.A.
 */

#ifndef _RTE_PCI_H_
#define _RTE_PCI_H_

#ifdef __cplusplus
extern "C" {
#endif

#include <stdio.h>
#include <limits.h>
#include <sys/queue.h>
#include <inttypes.h>

#define PCI_PRI_FMT "%.4" PRIx32 ":%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8
#define PCI_PRI_STR_SIZE sizeof("XXXXXXXX:XX:XX.X")

#define PCI_SHORT_PRI_FMT "%.2" PRIx8 ":%.2" PRIx8 ".%" PRIx8

#define PCI_FMT_NVAL 4

#define PCI_RESOURCE_FMT_NVAL 3

#define PCI_MAX_RESOURCE 6

struct rte_pci_id {
    uint32_t class_id;            
    uint16_t vendor_id;           
    uint16_t device_id;           
    uint16_t subsystem_vendor_id; 
    uint16_t subsystem_device_id; 
};

struct rte_pci_addr {
    uint32_t domain;                
    uint8_t bus;                    
    uint8_t devid;                  
    uint8_t function;               
};

#define PCI_ANY_ID (0xffff)
#define RTE_CLASS_ANY_ID (0xffffff)

struct pci_map {
    void *addr;
    char *path;
    uint64_t offset;
    uint64_t size;
    uint64_t phaddr;
};

struct pci_msix_table {
    int bar_index;
    uint32_t offset;
    uint32_t size;
};

struct mapped_pci_resource {
    TAILQ_ENTRY(mapped_pci_resource) next;

    struct rte_pci_addr pci_addr;
    char path[PATH_MAX];
    int nb_maps;
    struct pci_map maps[PCI_MAX_RESOURCE];
    struct pci_msix_table msix_table;
};


TAILQ_HEAD(mapped_pci_res_list, mapped_pci_resource);

void rte_pci_device_name(const struct rte_pci_addr *addr,
             char *output, size_t size);

int rte_pci_addr_cmp(const struct rte_pci_addr *addr,
             const struct rte_pci_addr *addr2);


int rte_pci_addr_parse(const char *str, struct rte_pci_addr *addr);

void *pci_map_resource(void *requested_addr, int fd, off_t offset,
        size_t size, int additional_flags);

void pci_unmap_resource(void *requested_addr, size_t size);

#ifdef __cplusplus
}
#endif

#endif /* _RTE_PCI_H_ */