5. Marvell OCTEON TX2 Platform Guide

This document gives an overview of Marvell OCTEON TX2 RVU H/W block, packet flow and procedure to build DPDK on OCTEON TX2 platform.

More information about OCTEON TX2 SoC can be found at Marvell Official Website.

5.1. Supported OCTEON TX2 SoCs

  • CN98xx
  • CN96xx
  • CN93xx

5.2. OCTEON TX2 Resource Virtualization Unit architecture

The Fig. 5.2 diagram depicts the RVU architecture and a resource provisioning example.


Fig. 5.2 OCTEON TX2 Resource virtualization architecture and provisioning example

Resource Virtualization Unit (RVU) on Marvell’s OCTEON TX2 SoC maps HW resources belonging to the network, crypto and other functional blocks onto PCI-compatible physical and virtual functions.

Each functional block has multiple local functions (LFs) for provisioning to different PCIe devices. RVU supports multiple PCIe SRIOV physical functions (PFs) and virtual functions (VFs).

The Table 5.6 shows the various local functions (LFs) provided by the RVU and its functional mapping to DPDK subsystem.

Table 5.6 RVU managed functional blocks and its mapping to DPDK subsystem
# LF DPDK subsystem mapping
1 NIX rte_ethdev, rte_tm, rte_event_eth_[rt]x_adapter, rte_security
2 NPA rte_mempool
3 NPC rte_flow
4 CPT rte_cryptodev, rte_event_crypto_adapter
5 SSO rte_eventdev
6 TIM rte_event_timer_adapter
7 LBK rte_ethdev
8 DPI rte_rawdev
9 SDP rte_ethdev
10 REE rte_regexdev

PF0 is called the administrative / admin function (AF) and has exclusive privileges to provision RVU functional block’s LFs to each of the PF/VF.

PF/VFs communicates with AF via a shared memory region (mailbox).Upon receiving requests from PF/VF, AF does resource provisioning and other HW configuration.

AF is always attached to host, but PF/VFs may be used by host kernel itself, or attached to VMs or to userspace applications like DPDK, etc. So, AF has to handle provisioning/configuration requests sent by any device from any domain.

The AF driver does not receive or process any data. It is only a configuration driver used in control path.

The Fig. 5.2 diagram also shows a resource provisioning example where,

  1. PFx and PFx-VF0 bound to Linux netdev driver.
  2. PFx-VF1 ethdev driver bound to the first DPDK application.
  3. PFy ethdev driver, PFy-VF0 ethdev driver, PFz eventdev driver, PFm-VF0 cryptodev driver bound to the second DPDK application.

5.3. LBK HW Access

Loopback HW Unit (LBK) receives packets from NIX-RX and sends packets back to NIX-TX. The loopback block has N channels and contains data buffering that is shared across all channels. The LBK HW Unit is abstracted using ethdev subsystem, Where PF0’s VFs are exposed as ethdev device and odd-even pairs of VFs are tied together, that is, packets sent on odd VF end up received on even VF and vice versa. This would enable HW accelerated means of communication between two domains where even VF bound to the first domain and odd VF bound to the second domain.

Typical application usage models are,

  1. Communication between the Linux kernel and DPDK application.
  2. Exception path to Linux kernel from DPDK application as SW KNI replacement.
  3. Communication between two different DPDK applications.

5.4. SDP interface

System DPI Packet Interface unit(SDP) provides PCIe endpoint support for remote host to DMA packets into and out of OCTEON TX2 SoC. SDP interface comes in to live only when OCTEON TX2 SoC is connected in PCIe endpoint mode. It can be used to send/receive packets to/from remote host machine using input/output queue pairs exposed to it. SDP interface receives input packets from remote host from NIX-RX and sends packets to remote host using NIX-TX. Remote host machine need to use corresponding driver (kernel/user mode) to communicate with SDP interface on OCTEON TX2 SoC. SDP supports single PCIe SRIOV physical function(PF) and multiple virtual functions(VF’s). Users can bind PF or VF to use SDP interface and it will be enumerated as ethdev ports.

The primary use case for SDP is to enable the smart NIC use case. Typical usage models are,

  1. Communication channel between remote host and OCTEON TX2 SoC over PCIe.
  2. Transfer packets received from network interface to remote host over PCIe and vice-versa.

5.5. OCTEON TX2 packet flow

The Fig. 5.3 diagram depicts the packet flow on OCTEON TX2 SoC in conjunction with use of various HW accelerators.


Fig. 5.3 OCTEON TX2 packet flow in conjunction with use of HW accelerators

5.6. HW Offload Drivers

This section lists dataplane H/W block(s) available in OCTEON TX2 SoC.

  1. Ethdev Driver See OCTEON TX2 Poll Mode driver for NIX Ethdev driver information.
  2. Mempool Driver See OCTEON TX2 NPA Mempool Driver for NPA mempool driver information.
  3. Event Device Driver See OCTEON TX2 SSO Eventdev Driver for SSO event device driver information.
  4. DMA Rawdev Driver See OCTEON TX2 DMA Driver for DMA driver information.
  5. Crypto Device Driver See Marvell OCTEON TX2 Crypto Poll Mode Driver for CPT crypto device driver information.
  6. Regex Device Driver See OCTEON TX2 REE Regexdev Driver for REE regex device driver information.

5.7. Procedure to Setup Platform

There are three main prerequisites for setting up DPDK on OCTEON TX2 compatible board:

  1. OCTEON TX2 Linux kernel driver

    The dependent kernel drivers can be obtained from the kernel.org.

    Alternatively, the Marvell SDK also provides the required kernel drivers.

    Linux kernel should be configured with the following features enabled:

# 64K pages enabled for better performance
# huge pages support enabled
# VFIO enabled with TYPE1 IOMMU at minimum
# SMMUv3 driver
# ARMv8.1 LSE atomics
# OCTEONTX2 drivers
# Enable if netdev PF driver required
# Enable if netdev VF driver required
# Enable if OCTEONTX2 DMA PF driver required
  1. ARM64 Linux Tool Chain

    For example, the aarch64 Linaro Toolchain, which can be obtained from here.

    Alternatively, the Marvell SDK also provides GNU GCC toolchain, which is optimized for OCTEON TX2 CPU.

  2. Rootfile system

    Any aarch64 supporting filesystem may be used. For example, Ubuntu 15.10 (Wily) or 16.04 LTS (Xenial) userland which can be obtained from http://cdimage.ubuntu.com/ubuntu-base/releases/16.04/release/ubuntu-base-16.04.1-base-arm64.tar.gz.

    Alternatively, the Marvell SDK provides the buildroot based root filesystem. The SDK includes all the above prerequisites necessary to bring up the OCTEON TX2 board.

5.8. Debugging Options

Table 5.7 OCTEON TX2 common debug options
# Component EAL log command
1 Common –log-level=’pmd.octeontx2.base,8’
2 Mailbox –log-level=’pmd.octeontx2.mbox,8’

5.8.1. Debugfs support

The OCTEON TX2 Linux kernel driver provides support to dump RVU blocks context or stats using debugfs.

Enable debugfs by:

  1. Compile kernel with debugfs enabled, i.e CONFIG_DEBUG_FS=y.
  2. Boot OCTEON TX2 with debugfs supported kernel.
  3. Verify debugfs mounted by default “mount | grep -i debugfs” or mount it manually by using.
# mount -t debugfs none /sys/kernel/debug

Currently debugfs supports the following RVU blocks NIX, NPA, NPC, NDC, SSO & CGX.

The file structure under /sys/kernel/debug is as follows

|-- cgx
|   |-- cgx0
|   |   '-- lmac0
|   |       '-- stats
|   |-- cgx1
|   |   |-- lmac0
|   |   |   '-- stats
|   |   '-- lmac1
|   |       '-- stats
|   '-- cgx2
|       '-- lmac0
|           '-- stats
|-- cpt
|   |-- cpt_engines_info
|   |-- cpt_engines_sts
|   |-- cpt_err_info
|   |-- cpt_lfs_info
|   '-- cpt_pc
|---- nix
|   |-- cq_ctx
|   |-- ndc_rx_cache
|   |-- ndc_rx_hits_miss
|   |-- ndc_tx_cache
|   |-- ndc_tx_hits_miss
|   |-- qsize
|   |-- rq_ctx
|   |-- sq_ctx
|   '-- tx_stall_hwissue
|-- npa
|   |-- aura_ctx
|   |-- ndc_cache
|   |-- ndc_hits_miss
|   |-- pool_ctx
|   '-- qsize
|-- npc
|    |-- mcam_info
|    '-- rx_miss_act_stats
|-- rsrc_alloc
'-- sso
     |-- hws
     |   '-- sso_hws_info
     '-- hwgrp
         |-- sso_hwgrp_aq_thresh
         |-- sso_hwgrp_iaq_walk
         |-- sso_hwgrp_pc
         |-- sso_hwgrp_free_list_walk
         |-- sso_hwgrp_ient_walk
         '-- sso_hwgrp_taq_walk

RVU block LF allocation:

cat /sys/kernel/debug/octeontx2/rsrc_alloc

pcifunc    NPA    NIX    SSO GROUP    SSOWS    TIM    CPT
PF1         0       0
PF4                 1
PF13                          0, 1     0, 1      0

CGX example usage:

cat /sys/kernel/debug/octeontx2/cgx/cgx2/lmac0/stats

=======Link Status======
Link is UP 40000 Mbps
Received packets: 0
Octets of received packets: 0
Received PAUSE packets: 0
Received PAUSE and control packets: 0
Filtered DMAC0 (NIX-bound) packets: 0
Filtered DMAC0 (NIX-bound) octets: 0
Packets dropped due to RX FIFO full: 0
Octets dropped due to RX FIFO full: 0
Error packets: 0
Filtered DMAC1 (NCSI-bound) packets: 0
Filtered DMAC1 (NCSI-bound) octets: 0
NCSI-bound packets dropped: 0
NCSI-bound octets dropped: 0
Packets dropped due to excessive collisions: 0
Packets dropped due to excessive deferral: 0
Multiple collisions before successful transmission: 0
Single collisions before successful transmission: 0
Total octets sent on the interface: 0
Total frames sent on the interface: 0
Packets sent with an octet count < 64: 0
Packets sent with an octet count == 64: 0
Packets sent with an octet count of 65127: 0
Packets sent with an octet count of 128-255: 0
Packets sent with an octet count of 256-511: 0
Packets sent with an octet count of 512-1023: 0
Packets sent with an octet count of 1024-1518: 0
Packets sent with an octet count of > 1518: 0
Packets sent to a broadcast DMAC: 0
Packets sent to the multicast DMAC: 0
Transmit underflow and were truncated: 0
Control/PAUSE packets sent: 0

CPT example usage:

cat /sys/kernel/debug/octeontx2/cpt/cpt_pc

CPT instruction requests   0
CPT instruction latency    0
CPT NCB read requests      0
CPT NCB read latency       0
CPT read requests caused by UC fills   0
CPT active cycles pc       1395642
CPT clock count pc         5579867595493

NIX example usage:

Usage: echo <nixlf> [cq number/all] > /sys/kernel/debug/octeontx2/nix/cq_ctx
       cat /sys/kernel/debug/octeontx2/nix/cq_ctx
echo 0 0 > /sys/kernel/debug/octeontx2/nix/cq_ctx
cat /sys/kernel/debug/octeontx2/nix/cq_ctx

=====cq_ctx for nixlf:0 and qidx:0 is=====
W0: base                        158ef1a00

W1: wrptr                       0
W1: avg_con                     0
W1: cint_idx                    0
W1: cq_err                      0
W1: qint_idx                    0
W1: bpid                        0
W1: bp_ena                      0

W2: update_time                 31043
W2:avg_level                    255
W2: head                        0
W2:tail                         0

W3: cq_err_int_ena              5
W3:cq_err_int                   0
W3: qsize                       4
W3:caching                      1
W3: substream                   0x000
W3: ena                                 1
W3: drop_ena                    1
W3: drop                        64
W3: bp                          0

NPA example usage:

Usage: echo <npalf> [pool number/all] > /sys/kernel/debug/octeontx2/npa/pool_ctx
       cat /sys/kernel/debug/octeontx2/npa/pool_ctx
echo 0 0 > /sys/kernel/debug/octeontx2/npa/pool_ctx
cat /sys/kernel/debug/octeontx2/npa/pool_ctx

======POOL : 0=======
W0: Stack base          1375bff00
W1: ena                 1
W1: nat_align           1
W1: stack_caching       1
W1: stack_way_mask      0
W1: buf_offset          1
W1: buf_size            19
W2: stack_max_pages     24315
W2: stack_pages         24314
W3: op_pc               267456
W4: stack_offset        2
W4: shift               5
W4: avg_level           255
W4: avg_con             0
W4: fc_ena              0
W4: fc_stype            0
W4: fc_hyst_bits        0
W4: fc_up_crossing      0
W4: update_time         62993
W5: fc_addr             0
W6: ptr_start           1593adf00
W7: ptr_end             180000000
W8: err_int             0
W8: err_int_ena         7
W8: thresh_int          0
W8: thresh_int_ena      0
W8: thresh_up           0
W8: thresh_qint_idx     0
W8: err_qint_idx        0

NPC example usage:

cat /sys/kernel/debug/octeontx2/npc/mcam_info

NPC MCAM info:
RX keywidth    : 224bits
TX keywidth    : 224bits

MCAM entries   : 2048
Reserved       : 158
Available      : 1890

MCAM counters  : 512
Reserved       : 1
Available      : 511

SSO example usage:

Usage: echo [<hws>/all] > /sys/kernel/debug/octeontx2/sso/hws/sso_hws_info
echo 0 > /sys/kernel/debug/octeontx2/sso/hws/sso_hws_info

SSOW HWS[0] Arbitration State      0x0
SSOW HWS[0] Guest Machine Control  0x0
SSOW HWS[0] SET[0] Group Mask[0] 0xffffffffffffffff
SSOW HWS[0] SET[0] Group Mask[1] 0xffffffffffffffff
SSOW HWS[0] SET[0] Group Mask[2] 0xffffffffffffffff
SSOW HWS[0] SET[0] Group Mask[3] 0xffffffffffffffff
SSOW HWS[0] SET[1] Group Mask[0] 0xffffffffffffffff
SSOW HWS[0] SET[1] Group Mask[1] 0xffffffffffffffff
SSOW HWS[0] SET[1] Group Mask[2] 0xffffffffffffffff
SSOW HWS[0] SET[1] Group Mask[3] 0xffffffffffffffff

5.9. Compile DPDK

DPDK may be compiled either natively on OCTEON TX2 platform or cross-compiled on an x86 based platform.

5.9.1. Native Compilation

meson setup build
ninja -C build

5.9.2. Cross Compilation

Refer to Cross compile DPDK for ARM64 for generic arm64 details.

meson setup build --cross-file config/arm/arm64_octeontx2_linux_gcc
ninja -C build


By default, meson cross compilation uses aarch64-linux-gnu-gcc toolchain, if Marvell toolchain is available then it can be used by overriding the c, cpp, ar, strip binaries attributes to respective Marvell toolchain binaries in config/arm/arm64_octeontx2_linux_gcc file.