5 #ifndef RTE_PMD_PRIVATE_MLX5_H_ 6 #define RTE_PMD_PRIVATE_MLX5_H_ 8 #include <rte_compat.h> 22 #define RTE_PMD_MLX5_FINE_GRANULARITY_INLINE "mlx5_fine_granularity_inline" 41 #define MLX5_DOMAIN_BIT_NIC_RX (1 << 0) 42 #define MLX5_DOMAIN_BIT_NIC_TX (1 << 1) 43 #define MLX5_DOMAIN_BIT_FDB (1 << 2) 69 #define MLX5_EXTERNAL_RX_QUEUE_ID_MIN (UINT16_MAX - 1000 + 1) 74 #define MLX5_LINEAR_HASH_TAG_INDEX 255 126 #define MLX5_HOST_SHAPER_FLAG_AVAIL_THRESH_TRIGGERED 0 167 enum mlx5_flow_engine_mode {
168 MLX5_FLOW_ENGINE_MODE_ACTIVE,
169 MLX5_FLOW_ENGINE_MODE_STANDBY,
176 #define MLX5_FLOW_ENGINE_FLAG_STANDBY_DUP_INGRESS RTE_BIT32(0) __rte_experimental int rte_pmd_mlx5_host_shaper_config(int port_id, uint8_t rate, uint32_t flags)
__rte_experimental int rte_pmd_mlx5_external_rx_queue_id_unmap(uint16_t port_id, uint16_t dpdk_idx)
__rte_experimental int rte_pmd_mlx5_external_sq_enable(uint16_t port_id, uint32_t sq_num)
__rte_experimental int rte_pmd_mlx5_sync_flow(uint16_t port_id, uint32_t domains)
__rte_experimental int rte_pmd_mlx5_get_dyn_flag_names(char *names[], unsigned int n)
__rte_experimental int rte_pmd_mlx5_external_rx_queue_id_map(uint16_t port_id, uint16_t dpdk_idx, uint32_t hw_idx)
__rte_experimental int rte_pmd_mlx5_flow_engine_set_mode(enum mlx5_flow_engine_mode mode, uint32_t flags)