DPDK  2.2.0
rte_eth_ctrl.h
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33 
34 #ifndef _RTE_ETH_CTRL_H_
35 #define _RTE_ETH_CTRL_H_
36 
45 #ifdef __cplusplus
46 extern "C" {
47 #endif
48 
49 /*
50  * A packet can be identified by hardware as different flow types. Different
51  * NIC hardwares may support different flow types.
52  * Basically, the NIC hardware identifies the flow type as deep protocol as
53  * possible, and exclusively. For example, if a packet is identified as
54  * 'RTE_ETH_FLOW_NONFRAG_IPV4_TCP', it will not be any of other flow types,
55  * though it is an actual IPV4 packet.
56  * Note that the flow types are used to define RSS offload types in
57  * rte_ethdev.h.
58  */
59 #define RTE_ETH_FLOW_UNKNOWN 0
60 #define RTE_ETH_FLOW_RAW 1
61 #define RTE_ETH_FLOW_IPV4 2
62 #define RTE_ETH_FLOW_FRAG_IPV4 3
63 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4
64 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5
65 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6
66 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7
67 #define RTE_ETH_FLOW_IPV6 8
68 #define RTE_ETH_FLOW_FRAG_IPV6 9
69 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10
70 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11
71 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12
72 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13
73 #define RTE_ETH_FLOW_L2_PAYLOAD 14
74 #define RTE_ETH_FLOW_IPV6_EX 15
75 #define RTE_ETH_FLOW_IPV6_TCP_EX 16
76 #define RTE_ETH_FLOW_IPV6_UDP_EX 17
77 #define RTE_ETH_FLOW_MAX 18
78 
82 enum rte_filter_type {
83  RTE_ETH_FILTER_NONE = 0,
84  RTE_ETH_FILTER_MACVLAN,
85  RTE_ETH_FILTER_ETHERTYPE,
86  RTE_ETH_FILTER_FLEXIBLE,
87  RTE_ETH_FILTER_SYN,
88  RTE_ETH_FILTER_NTUPLE,
89  RTE_ETH_FILTER_TUNNEL,
90  RTE_ETH_FILTER_FDIR,
91  RTE_ETH_FILTER_HASH,
92  RTE_ETH_FILTER_MAX
93 };
94 
98 enum rte_filter_op {
100  RTE_ETH_FILTER_NOP = 0,
101  RTE_ETH_FILTER_ADD,
102  RTE_ETH_FILTER_UPDATE,
103  RTE_ETH_FILTER_DELETE,
104  RTE_ETH_FILTER_FLUSH,
105  RTE_ETH_FILTER_GET,
106  RTE_ETH_FILTER_SET,
107  RTE_ETH_FILTER_INFO,
108  RTE_ETH_FILTER_STATS,
109  RTE_ETH_FILTER_OP_MAX
110 };
111 
115 enum rte_mac_filter_type {
116  RTE_MAC_PERFECT_MATCH = 1,
117  RTE_MACVLAN_PERFECT_MATCH,
118  RTE_MAC_HASH_MATCH,
120  RTE_MACVLAN_HASH_MATCH,
121 };
122 
126 struct rte_eth_mac_filter {
127  uint8_t is_vf;
128  uint16_t dst_id;
129  enum rte_mac_filter_type filter_type;
130  struct ether_addr mac_addr;
131 };
132 
137 #define RTE_ETHTYPE_FLAGS_MAC 0x0001
138 #define RTE_ETHTYPE_FLAGS_DROP 0x0002
145 struct rte_eth_ethertype_filter {
146  struct ether_addr mac_addr;
147  uint16_t ether_type;
148  uint16_t flags;
149  uint16_t queue;
150 };
151 
152 #define RTE_FLEX_FILTER_MAXLEN 128
153 #define RTE_FLEX_FILTER_MASK_SIZE \
154  (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
155 
162 struct rte_eth_flex_filter {
163  uint16_t len;
164  uint8_t bytes[RTE_FLEX_FILTER_MAXLEN];
165  uint8_t mask[RTE_FLEX_FILTER_MASK_SIZE];
167  uint8_t priority;
168  uint16_t queue;
169 };
170 
176 struct rte_eth_syn_filter {
177  uint8_t hig_pri;
179  uint16_t queue;
180 };
181 
186 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
187 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
188 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
189 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
190 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
191 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
193 #define RTE_5TUPLE_FLAGS ( \
194  RTE_NTUPLE_FLAGS_DST_IP | \
195  RTE_NTUPLE_FLAGS_SRC_IP | \
196  RTE_NTUPLE_FLAGS_DST_PORT | \
197  RTE_NTUPLE_FLAGS_SRC_PORT | \
198  RTE_NTUPLE_FLAGS_PROTO)
199 
200 #define RTE_2TUPLE_FLAGS ( \
201  RTE_NTUPLE_FLAGS_DST_PORT | \
202  RTE_NTUPLE_FLAGS_PROTO)
203 
204 #define TCP_URG_FLAG 0x20
205 #define TCP_ACK_FLAG 0x10
206 #define TCP_PSH_FLAG 0x08
207 #define TCP_RST_FLAG 0x04
208 #define TCP_SYN_FLAG 0x02
209 #define TCP_FIN_FLAG 0x01
210 #define TCP_FLAG_ALL 0x3F
211 
217 struct rte_eth_ntuple_filter {
218  uint16_t flags;
219  uint32_t dst_ip;
220  uint32_t dst_ip_mask;
221  uint32_t src_ip;
222  uint32_t src_ip_mask;
223  uint16_t dst_port;
224  uint16_t dst_port_mask;
225  uint16_t src_port;
226  uint16_t src_port_mask;
227  uint8_t proto;
228  uint8_t proto_mask;
232  uint8_t tcp_flags;
233  uint16_t priority;
235  uint16_t queue;
236 };
237 
241 enum rte_eth_tunnel_type {
242  RTE_TUNNEL_TYPE_NONE = 0,
243  RTE_TUNNEL_TYPE_VXLAN,
244  RTE_TUNNEL_TYPE_GENEVE,
245  RTE_TUNNEL_TYPE_TEREDO,
246  RTE_TUNNEL_TYPE_NVGRE,
247  RTE_TUNNEL_TYPE_MAX,
248 };
249 
253 #define ETH_TUNNEL_FILTER_OMAC 0x01
254 #define ETH_TUNNEL_FILTER_OIP 0x02
255 #define ETH_TUNNEL_FILTER_TENID 0x04
256 #define ETH_TUNNEL_FILTER_IMAC 0x08
257 #define ETH_TUNNEL_FILTER_IVLAN 0x10
258 #define ETH_TUNNEL_FILTER_IIP 0x20
260 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
261  ETH_TUNNEL_FILTER_IVLAN)
262 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
263  ETH_TUNNEL_FILTER_IVLAN | \
264  ETH_TUNNEL_FILTER_TENID)
265 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
266  ETH_TUNNEL_FILTER_TENID)
267 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
268  ETH_TUNNEL_FILTER_TENID | \
269  ETH_TUNNEL_FILTER_IMAC)
270 
274 enum rte_tunnel_iptype {
275  RTE_TUNNEL_IPTYPE_IPV4 = 0,
276  RTE_TUNNEL_IPTYPE_IPV6,
277 };
278 
282 struct rte_eth_tunnel_filter_conf {
283  struct ether_addr *outer_mac;
284  struct ether_addr *inner_mac;
285  uint16_t inner_vlan;
286  enum rte_tunnel_iptype ip_type;
287  union {
288  uint32_t ipv4_addr;
289  uint32_t ipv6_addr[4];
290  } ip_addr;
292  uint16_t filter_type;
293  enum rte_eth_tunnel_type tunnel_type;
294  uint32_t tenant_id;
295  uint16_t queue_id;
296 };
297 
301 enum rte_eth_global_cfg_type {
302  RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
303  RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
304  RTE_ETH_GLOBAL_CFG_TYPE_MAX,
305 };
306 
310 struct rte_eth_global_cfg {
311  enum rte_eth_global_cfg_type cfg_type;
312  union {
313  uint8_t gre_key_len;
314  uint64_t reserved;
315  } cfg;
316 };
317 
318 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
319 #define RTE_ETH_INSET_SIZE_MAX 128
324 enum rte_eth_input_set_field {
325  RTE_ETH_INPUT_SET_UNKNOWN = 0,
326 
327  /* L2 */
328  RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
329  RTE_ETH_INPUT_SET_L2_DST_MAC,
330  RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
331  RTE_ETH_INPUT_SET_L2_INNER_VLAN,
332  RTE_ETH_INPUT_SET_L2_ETHERTYPE,
333 
334  /* L3 */
335  RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
336  RTE_ETH_INPUT_SET_L3_DST_IP4,
337  RTE_ETH_INPUT_SET_L3_SRC_IP6,
338  RTE_ETH_INPUT_SET_L3_DST_IP6,
339  RTE_ETH_INPUT_SET_L3_IP4_TOS,
340  RTE_ETH_INPUT_SET_L3_IP4_PROTO,
341  RTE_ETH_INPUT_SET_L3_IP6_TC,
342  RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
343 
344  /* L4 */
345  RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
346  RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
347  RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
348  RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
349  RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
350  RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
351  RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
352 
353  /* Tunnel */
354  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
355  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
356  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
357  RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
358  RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
359 
360  /* Flexible Payload */
361  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
362  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
363  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
364  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
365  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
366  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
367  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
368  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
369 
370  RTE_ETH_INPUT_SET_DEFAULT = 65533,
371  RTE_ETH_INPUT_SET_NONE = 65534,
372  RTE_ETH_INPUT_SET_MAX = 65535,
373 };
374 
378 enum rte_filter_input_set_op {
379  RTE_ETH_INPUT_SET_OP_UNKNOWN,
380  RTE_ETH_INPUT_SET_SELECT,
381  RTE_ETH_INPUT_SET_ADD,
382  RTE_ETH_INPUT_SET_OP_MAX
383 };
384 
385 
390 struct rte_eth_input_set_conf {
391  uint16_t flow_type;
392  uint16_t inset_size;
393  enum rte_eth_input_set_field field[RTE_ETH_INSET_SIZE_MAX];
394  enum rte_filter_input_set_op op;
395 };
396 
400 struct rte_eth_l2_flow {
401  uint16_t ether_type;
402 };
403 
407 struct rte_eth_ipv4_flow {
408  uint32_t src_ip;
409  uint32_t dst_ip;
410 };
411 
415 struct rte_eth_udpv4_flow {
416  struct rte_eth_ipv4_flow ip;
417  uint16_t src_port;
418  uint16_t dst_port;
419 };
420 
424 struct rte_eth_tcpv4_flow {
425  struct rte_eth_ipv4_flow ip;
426  uint16_t src_port;
427  uint16_t dst_port;
428 };
429 
433 struct rte_eth_sctpv4_flow {
434  struct rte_eth_ipv4_flow ip;
435  uint16_t src_port;
436  uint16_t dst_port;
437  uint32_t verify_tag;
438 };
439 
443 struct rte_eth_ipv6_flow {
444  uint32_t src_ip[4];
445  uint32_t dst_ip[4];
446 };
447 
451 struct rte_eth_udpv6_flow {
452  struct rte_eth_ipv6_flow ip;
453  uint16_t src_port;
454  uint16_t dst_port;
455 };
456 
460 struct rte_eth_tcpv6_flow {
461  struct rte_eth_ipv6_flow ip;
462  uint16_t src_port;
463  uint16_t dst_port;
464 };
465 
469 struct rte_eth_sctpv6_flow {
470  struct rte_eth_ipv6_flow ip;
471  uint16_t src_port;
472  uint16_t dst_port;
473  uint32_t verify_tag;
474 };
475 
479 struct rte_eth_mac_vlan_flow {
480  struct ether_addr mac_addr;
481 };
482 
486 enum rte_eth_fdir_tunnel_type {
487  RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
488  RTE_FDIR_TUNNEL_TYPE_NVGRE,
489  RTE_FDIR_TUNNEL_TYPE_VXLAN,
490 };
491 
496 struct rte_eth_tunnel_flow {
497  enum rte_eth_fdir_tunnel_type tunnel_type;
498  uint32_t tunnel_id;
499  struct ether_addr mac_addr;
500 };
501 
505 union rte_eth_fdir_flow {
506  struct rte_eth_l2_flow l2_flow;
507  struct rte_eth_udpv4_flow udp4_flow;
508  struct rte_eth_tcpv4_flow tcp4_flow;
509  struct rte_eth_sctpv4_flow sctp4_flow;
510  struct rte_eth_ipv4_flow ip4_flow;
511  struct rte_eth_udpv6_flow udp6_flow;
512  struct rte_eth_tcpv6_flow tcp6_flow;
513  struct rte_eth_sctpv6_flow sctp6_flow;
514  struct rte_eth_ipv6_flow ipv6_flow;
515  struct rte_eth_mac_vlan_flow mac_vlan_flow;
516  struct rte_eth_tunnel_flow tunnel_flow;
517 };
518 
522 struct rte_eth_fdir_flow_ext {
523  uint16_t vlan_tci;
524  uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
526  uint8_t is_vf;
527  uint16_t dst_id;
528 };
529 
533 struct rte_eth_fdir_input {
534  uint16_t flow_type;
535  union rte_eth_fdir_flow flow;
537  struct rte_eth_fdir_flow_ext flow_ext;
539 };
540 
544 enum rte_eth_fdir_behavior {
545  RTE_ETH_FDIR_ACCEPT = 0,
546  RTE_ETH_FDIR_REJECT,
547  RTE_ETH_FDIR_PASSTHRU,
548 };
549 
554 enum rte_eth_fdir_status {
555  RTE_ETH_FDIR_NO_REPORT_STATUS = 0,
556  RTE_ETH_FDIR_REPORT_ID,
557  RTE_ETH_FDIR_REPORT_ID_FLEX_4,
558  RTE_ETH_FDIR_REPORT_FLEX_8,
559 };
560 
564 struct rte_eth_fdir_action {
565  uint16_t rx_queue;
566  enum rte_eth_fdir_behavior behavior;
567  enum rte_eth_fdir_status report_status;
568  uint8_t flex_off;
572 };
573 
579 struct rte_eth_fdir_filter {
580  uint32_t soft_id;
582  struct rte_eth_fdir_input input;
583  struct rte_eth_fdir_action action;
584 };
585 
590 struct rte_eth_fdir_masks {
591  uint16_t vlan_tci_mask;
592  struct rte_eth_ipv4_flow ipv4_mask;
593  struct rte_eth_ipv6_flow ipv6_mask;
594  uint16_t src_port_mask;
595  uint16_t dst_port_mask;
596  uint8_t mac_addr_byte_mask;
597  uint32_t tunnel_id_mask;
598  uint8_t tunnel_type_mask;
599 };
600 
604 enum rte_eth_payload_type {
605  RTE_ETH_PAYLOAD_UNKNOWN = 0,
606  RTE_ETH_RAW_PAYLOAD,
607  RTE_ETH_L2_PAYLOAD,
608  RTE_ETH_L3_PAYLOAD,
609  RTE_ETH_L4_PAYLOAD,
610  RTE_ETH_PAYLOAD_MAX = 8,
611 };
612 
617 struct rte_eth_flex_payload_cfg {
618  enum rte_eth_payload_type type;
619  uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN];
624 };
625 
630 struct rte_eth_fdir_flex_mask {
631  uint16_t flow_type;
632  uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN];
634 };
635 
640 struct rte_eth_fdir_flex_conf {
641  uint16_t nb_payloads;
642  uint16_t nb_flexmasks;
643  struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
645  struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
647 };
648 
652 enum rte_fdir_mode {
653  RTE_FDIR_MODE_NONE = 0,
654  RTE_FDIR_MODE_SIGNATURE,
655  RTE_FDIR_MODE_PERFECT,
656  RTE_FDIR_MODE_PERFECT_MAC_VLAN,
657  RTE_FDIR_MODE_PERFECT_TUNNEL,
658 };
659 
660 #define UINT32_BIT (CHAR_BIT * sizeof(uint32_t))
661 #define RTE_FLOW_MASK_ARRAY_SIZE \
662  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)
663 
671 struct rte_eth_fdir_info {
672  enum rte_fdir_mode mode;
673  struct rte_eth_fdir_masks mask;
675  struct rte_eth_fdir_flex_conf flex_conf;
676  uint32_t guarant_spc;
677  uint32_t best_spc;
679  uint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
680  uint32_t max_flexpayload;
683  uint32_t flex_payload_unit;
686  uint32_t max_flex_payload_segment_num;
690  uint16_t flex_payload_limit;
693  uint32_t flex_bitmask_unit;
695  uint32_t max_flex_bitmask_num;
696 };
697 
702 struct rte_eth_fdir_stats {
703  uint32_t collision;
704  uint32_t free;
705  uint32_t maxhash;
708  uint32_t maxlen;
709  uint64_t add;
710  uint64_t remove;
711  uint64_t f_add;
712  uint64_t f_remove;
713  uint32_t guarant_cnt;
714  uint32_t best_cnt;
715 };
716 
720 enum rte_eth_fdir_filter_info_type {
721  RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
723  RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT,
724  RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
725 };
726 
731 struct rte_eth_fdir_filter_info {
732  enum rte_eth_fdir_filter_info_type info_type;
734  union {
736  struct rte_eth_input_set_conf input_set_conf;
737  } info;
738 };
739 
750 enum rte_eth_hash_filter_info_type {
751  RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
753  RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT,
755  RTE_ETH_HASH_FILTER_GLOBAL_CONFIG,
757  RTE_ETH_HASH_FILTER_INPUT_SET_SELECT,
758  RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
759 };
760 
764 enum rte_eth_hash_function {
765  RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
766  RTE_ETH_HASH_FUNCTION_TOEPLITZ,
767  RTE_ETH_HASH_FUNCTION_SIMPLE_XOR,
768  RTE_ETH_HASH_FUNCTION_MAX,
769 };
770 
771 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \
772  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)
773 
782 struct rte_eth_hash_global_conf {
783  enum rte_eth_hash_function hash_func;
785  uint32_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
787  uint32_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
788 };
789 
794 struct rte_eth_hash_filter_info {
795  enum rte_eth_hash_filter_info_type info_type;
797  union {
799  uint8_t enable;
801  struct rte_eth_hash_global_conf global_conf;
803  struct rte_eth_input_set_conf input_set_conf;
804  } info;
805 };
806 
807 #ifdef __cplusplus
808 }
809 #endif
810 
811 #endif /* _RTE_ETH_CTRL_H_ */
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