72 RTE_PMD_I40E_PKG_OP_UNDEFINED = 0,
76 RTE_PMD_I40E_PKG_OP_MAX = 32
83 RTE_PMD_I40E_PKG_INFO_UNDEFINED = 0,
84 RTE_PMD_I40E_PKG_INFO_GLOBAL_HEADER,
85 RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES_SIZE,
86 RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES,
87 RTE_PMD_I40E_PKG_INFO_GLOBAL_MAX = 1024,
88 RTE_PMD_I40E_PKG_INFO_HEADER,
89 RTE_PMD_I40E_PKG_INFO_DEVID_NUM,
90 RTE_PMD_I40E_PKG_INFO_DEVID_LIST,
91 RTE_PMD_I40E_PKG_INFO_MAX = 0xFFFFFFFF
94 #define RTE_PMD_I40E_DDP_NAME_SIZE 32
111 uint32_t vendor_dev_id;
112 uint32_t sub_vendor_dev_id;
123 uint8_t name[RTE_PMD_I40E_DDP_NAME_SIZE];
126 #define RTE_PMD_I40E_DDP_OWNER_UNKNOWN 0xFF
141 #define RTE_PMD_I40E_PTYPE_USER_DEFINE_MASK 0x80000000
143 struct rte_pmd_i40e_ptype_mapping {
372 uint64_t vf_mask, uint8_t on);
548 uint8_t *info, uint32_t size,
585 struct rte_pmd_i40e_ptype_mapping *mapping_items,
616 struct rte_pmd_i40e_ptype_mapping *mapping_items,