rte_memory.h

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/*-
 *   BSD LICENSE
 *
 *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
 *   All rights reserved.
 *
 *   Redistribution and use in source and binary forms, with or without
 *   modification, are permitted provided that the following conditions
 *   are met:
 *
 *     * Redistributions of source code must retain the above copyright
 *       notice, this list of conditions and the following disclaimer.
 *     * Redistributions in binary form must reproduce the above copyright
 *       notice, this list of conditions and the following disclaimer in
 *       the documentation and/or other materials provided with the
 *       distribution.
 *     * Neither the name of Intel Corporation nor the names of its
 *       contributors may be used to endorse or promote products derived
 *       from this software without specific prior written permission.
 *
 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef _RTE_MEMORY_H_
#define _RTE_MEMORY_H_

#include <stdint.h>
#include <stddef.h>
#include <stdio.h>

#include <rte_config.h>

#ifdef RTE_EXEC_ENV_LINUXAPP
#include <exec-env/rte_dom0_common.h>
#endif

#ifdef __cplusplus
extern "C" {
#endif

#include <rte_common.h>

__extension__
enum rte_page_sizes {
        RTE_PGSIZE_4K    = 1ULL << 12,
        RTE_PGSIZE_64K   = 1ULL << 16,
        RTE_PGSIZE_256K  = 1ULL << 18,
        RTE_PGSIZE_2M    = 1ULL << 21,
        RTE_PGSIZE_16M   = 1ULL << 24,
        RTE_PGSIZE_256M  = 1ULL << 28,
        RTE_PGSIZE_512M  = 1ULL << 29,
        RTE_PGSIZE_1G    = 1ULL << 30,
        RTE_PGSIZE_4G    = 1ULL << 32,
        RTE_PGSIZE_16G   = 1ULL << 34,
};

#define SOCKET_ID_ANY -1                    
#define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1) 
#define RTE_CACHE_LINE_ROUNDUP(size) \
        (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))

#if RTE_CACHE_LINE_SIZE == 64
#define RTE_CACHE_LINE_SIZE_LOG2 6
#elif RTE_CACHE_LINE_SIZE == 128
#define RTE_CACHE_LINE_SIZE_LOG2 7
#else
#error "Unsupported cache line size"
#endif

#define RTE_CACHE_LINE_MIN_SIZE 64      
#define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE)

#define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)

typedef uint64_t phys_addr_t; 
#define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1)

struct rte_memseg {
        phys_addr_t phys_addr;      
        RTE_STD_C11
        union {
                void *addr;         
                uint64_t addr_64;   
        };
        size_t len;               
        uint64_t hugepage_sz;       
        int32_t socket_id;          
        uint32_t nchannel;          
        uint32_t nrank;             
#ifdef RTE_LIBRTE_XEN_DOM0

        uint64_t mfn[DOM0_NUM_MEMBLOCK];
#endif
} __rte_packed;

int rte_mem_lock_page(const void *virt);

phys_addr_t rte_mem_virt2phy(const void *virt);

const struct rte_memseg *rte_eal_get_physmem_layout(void);

void rte_dump_physmem_layout(FILE *f);

uint64_t rte_eal_get_physmem_size(void);

unsigned rte_memory_get_nchannel(void);

unsigned rte_memory_get_nrank(void);

#ifdef RTE_LIBRTE_XEN_DOM0

int rte_xen_dom0_supported(void);

phys_addr_t rte_xen_mem_phy2mch(int32_t, const phys_addr_t);

static inline phys_addr_t
rte_mem_phy2mch(int32_t memseg_id, const phys_addr_t phy_addr)
{
        if (rte_xen_dom0_supported())
                return rte_xen_mem_phy2mch(memseg_id, phy_addr);
        else
                return phy_addr;
}

int rte_xen_dom0_memory_init(void);

int rte_xen_dom0_memory_attach(void);
#else
static inline int rte_xen_dom0_supported(void)
{
        return 0;
}

static inline phys_addr_t
rte_mem_phy2mch(int32_t memseg_id __rte_unused, const phys_addr_t phy_addr)
{
        return phy_addr;
}
#endif

#ifdef __cplusplus
}
#endif

#endif /* _RTE_MEMORY_H_ */