DPDK  17.05.2
rte_eth_ctrl.h
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1 /*-
2  * BSD LICENSE
3  *
4  * Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5  * All rights reserved.
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33 
34 #ifndef _RTE_ETH_CTRL_H_
35 #define _RTE_ETH_CTRL_H_
36 
37 #include <stdint.h>
38 #include <rte_common.h>
39 #include "rte_ether.h"
40 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
53 /*
54  * A packet can be identified by hardware as different flow types. Different
55  * NIC hardwares may support different flow types.
56  * Basically, the NIC hardware identifies the flow type as deep protocol as
57  * possible, and exclusively. For example, if a packet is identified as
58  * 'RTE_ETH_FLOW_NONFRAG_IPV4_TCP', it will not be any of other flow types,
59  * though it is an actual IPV4 packet.
60  * Note that the flow types are used to define RSS offload types in
61  * rte_ethdev.h.
62  */
63 #define RTE_ETH_FLOW_UNKNOWN 0
64 #define RTE_ETH_FLOW_RAW 1
65 #define RTE_ETH_FLOW_IPV4 2
66 #define RTE_ETH_FLOW_FRAG_IPV4 3
67 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4
68 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5
69 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6
70 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7
71 #define RTE_ETH_FLOW_IPV6 8
72 #define RTE_ETH_FLOW_FRAG_IPV6 9
73 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10
74 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11
75 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12
76 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13
77 #define RTE_ETH_FLOW_L2_PAYLOAD 14
78 #define RTE_ETH_FLOW_IPV6_EX 15
79 #define RTE_ETH_FLOW_IPV6_TCP_EX 16
80 #define RTE_ETH_FLOW_IPV6_UDP_EX 17
81 #define RTE_ETH_FLOW_PORT 18
82 
83 #define RTE_ETH_FLOW_VXLAN 19
84 #define RTE_ETH_FLOW_GENEVE 20
85 #define RTE_ETH_FLOW_NVGRE 21
86 #define RTE_ETH_FLOW_MAX 22
87 
91 enum rte_filter_type {
92  RTE_ETH_FILTER_NONE = 0,
93  RTE_ETH_FILTER_MACVLAN,
94  RTE_ETH_FILTER_ETHERTYPE,
95  RTE_ETH_FILTER_FLEXIBLE,
96  RTE_ETH_FILTER_SYN,
97  RTE_ETH_FILTER_NTUPLE,
98  RTE_ETH_FILTER_TUNNEL,
99  RTE_ETH_FILTER_FDIR,
100  RTE_ETH_FILTER_HASH,
101  RTE_ETH_FILTER_L2_TUNNEL,
102  RTE_ETH_FILTER_GENERIC,
103  RTE_ETH_FILTER_MAX
104 };
105 
109 enum rte_filter_op {
111  RTE_ETH_FILTER_NOP = 0,
112  RTE_ETH_FILTER_ADD,
113  RTE_ETH_FILTER_UPDATE,
114  RTE_ETH_FILTER_DELETE,
115  RTE_ETH_FILTER_FLUSH,
116  RTE_ETH_FILTER_GET,
117  RTE_ETH_FILTER_SET,
118  RTE_ETH_FILTER_INFO,
119  RTE_ETH_FILTER_STATS,
120  RTE_ETH_FILTER_OP_MAX
121 };
122 
126 enum rte_mac_filter_type {
127  RTE_MAC_PERFECT_MATCH = 1,
128  RTE_MACVLAN_PERFECT_MATCH,
129  RTE_MAC_HASH_MATCH,
131  RTE_MACVLAN_HASH_MATCH,
132 };
133 
137 struct rte_eth_mac_filter {
138  uint8_t is_vf;
139  uint16_t dst_id;
140  enum rte_mac_filter_type filter_type;
141  struct ether_addr mac_addr;
142 };
143 
148 #define RTE_ETHTYPE_FLAGS_MAC 0x0001
149 #define RTE_ETHTYPE_FLAGS_DROP 0x0002
156 struct rte_eth_ethertype_filter {
157  struct ether_addr mac_addr;
158  uint16_t ether_type;
159  uint16_t flags;
160  uint16_t queue;
161 };
162 
163 #define RTE_FLEX_FILTER_MAXLEN 128
164 #define RTE_FLEX_FILTER_MASK_SIZE \
165  (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
166 
173 struct rte_eth_flex_filter {
174  uint16_t len;
175  uint8_t bytes[RTE_FLEX_FILTER_MAXLEN];
176  uint8_t mask[RTE_FLEX_FILTER_MASK_SIZE];
178  uint8_t priority;
179  uint16_t queue;
180 };
181 
187 struct rte_eth_syn_filter {
188  uint8_t hig_pri;
190  uint16_t queue;
191 };
192 
197 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
198 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
199 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
200 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
201 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
202 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
204 #define RTE_5TUPLE_FLAGS ( \
205  RTE_NTUPLE_FLAGS_DST_IP | \
206  RTE_NTUPLE_FLAGS_SRC_IP | \
207  RTE_NTUPLE_FLAGS_DST_PORT | \
208  RTE_NTUPLE_FLAGS_SRC_PORT | \
209  RTE_NTUPLE_FLAGS_PROTO)
210 
211 #define RTE_2TUPLE_FLAGS ( \
212  RTE_NTUPLE_FLAGS_DST_PORT | \
213  RTE_NTUPLE_FLAGS_PROTO)
214 
215 #define TCP_URG_FLAG 0x20
216 #define TCP_ACK_FLAG 0x10
217 #define TCP_PSH_FLAG 0x08
218 #define TCP_RST_FLAG 0x04
219 #define TCP_SYN_FLAG 0x02
220 #define TCP_FIN_FLAG 0x01
221 #define TCP_FLAG_ALL 0x3F
222 
228 struct rte_eth_ntuple_filter {
229  uint16_t flags;
230  uint32_t dst_ip;
231  uint32_t dst_ip_mask;
232  uint32_t src_ip;
233  uint32_t src_ip_mask;
234  uint16_t dst_port;
235  uint16_t dst_port_mask;
236  uint16_t src_port;
237  uint16_t src_port_mask;
238  uint8_t proto;
239  uint8_t proto_mask;
243  uint8_t tcp_flags;
244  uint16_t priority;
246  uint16_t queue;
247 };
248 
252 enum rte_eth_tunnel_type {
253  RTE_TUNNEL_TYPE_NONE = 0,
254  RTE_TUNNEL_TYPE_VXLAN,
255  RTE_TUNNEL_TYPE_GENEVE,
256  RTE_TUNNEL_TYPE_TEREDO,
257  RTE_TUNNEL_TYPE_NVGRE,
258  RTE_TUNNEL_TYPE_IP_IN_GRE,
259  RTE_L2_TUNNEL_TYPE_E_TAG,
260  RTE_TUNNEL_TYPE_MAX,
261 };
262 
266 #define ETH_TUNNEL_FILTER_OMAC 0x01
267 #define ETH_TUNNEL_FILTER_OIP 0x02
268 #define ETH_TUNNEL_FILTER_TENID 0x04
269 #define ETH_TUNNEL_FILTER_IMAC 0x08
270 #define ETH_TUNNEL_FILTER_IVLAN 0x10
271 #define ETH_TUNNEL_FILTER_IIP 0x20
273 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
274  ETH_TUNNEL_FILTER_IVLAN)
275 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
276  ETH_TUNNEL_FILTER_IVLAN | \
277  ETH_TUNNEL_FILTER_TENID)
278 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
279  ETH_TUNNEL_FILTER_TENID)
280 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
281  ETH_TUNNEL_FILTER_TENID | \
282  ETH_TUNNEL_FILTER_IMAC)
283 
287 enum rte_tunnel_iptype {
288  RTE_TUNNEL_IPTYPE_IPV4 = 0,
289  RTE_TUNNEL_IPTYPE_IPV6,
290 };
291 
295 struct rte_eth_tunnel_filter_conf {
296  struct ether_addr outer_mac;
297  struct ether_addr inner_mac;
298  uint16_t inner_vlan;
299  enum rte_tunnel_iptype ip_type;
303  union {
304  uint32_t ipv4_addr;
305  uint32_t ipv6_addr[4];
306  } ip_addr;
308  uint16_t filter_type;
309  enum rte_eth_tunnel_type tunnel_type;
310  uint32_t tenant_id;
311  uint16_t queue_id;
312 };
313 
317 enum rte_eth_global_cfg_type {
318  RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
319  RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
320  RTE_ETH_GLOBAL_CFG_TYPE_MAX,
321 };
322 
326 struct rte_eth_global_cfg {
327  enum rte_eth_global_cfg_type cfg_type;
328  union {
329  uint8_t gre_key_len;
330  uint64_t reserved;
331  } cfg;
332 };
333 
334 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
335 #define RTE_ETH_INSET_SIZE_MAX 128
340 enum rte_eth_input_set_field {
341  RTE_ETH_INPUT_SET_UNKNOWN = 0,
342 
343  /* L2 */
344  RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
345  RTE_ETH_INPUT_SET_L2_DST_MAC,
346  RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
347  RTE_ETH_INPUT_SET_L2_INNER_VLAN,
348  RTE_ETH_INPUT_SET_L2_ETHERTYPE,
349 
350  /* L3 */
351  RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
352  RTE_ETH_INPUT_SET_L3_DST_IP4,
353  RTE_ETH_INPUT_SET_L3_SRC_IP6,
354  RTE_ETH_INPUT_SET_L3_DST_IP6,
355  RTE_ETH_INPUT_SET_L3_IP4_TOS,
356  RTE_ETH_INPUT_SET_L3_IP4_PROTO,
357  RTE_ETH_INPUT_SET_L3_IP6_TC,
358  RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
359  RTE_ETH_INPUT_SET_L3_IP4_TTL,
360  RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
361 
362  /* L4 */
363  RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
364  RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
365  RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
366  RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
367  RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
368  RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
369  RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
370 
371  /* Tunnel */
372  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
373  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
374  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
375  RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
376  RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
377 
378  /* Flexible Payload */
379  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
380  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
381  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
382  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
383  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
384  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
385  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
386  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
387 
388  RTE_ETH_INPUT_SET_DEFAULT = 65533,
389  RTE_ETH_INPUT_SET_NONE = 65534,
390  RTE_ETH_INPUT_SET_MAX = 65535,
391 };
392 
396 enum rte_filter_input_set_op {
397  RTE_ETH_INPUT_SET_OP_UNKNOWN,
398  RTE_ETH_INPUT_SET_SELECT,
399  RTE_ETH_INPUT_SET_ADD,
400  RTE_ETH_INPUT_SET_OP_MAX
401 };
402 
403 
408 struct rte_eth_input_set_conf {
409  uint16_t flow_type;
410  uint16_t inset_size;
411  enum rte_eth_input_set_field field[RTE_ETH_INSET_SIZE_MAX];
412  enum rte_filter_input_set_op op;
413 };
414 
418 struct rte_eth_l2_flow {
419  uint16_t ether_type;
420 };
421 
425 struct rte_eth_ipv4_flow {
426  uint32_t src_ip;
427  uint32_t dst_ip;
428  uint8_t tos;
429  uint8_t ttl;
430  uint8_t proto;
431 };
432 
436 struct rte_eth_udpv4_flow {
437  struct rte_eth_ipv4_flow ip;
438  uint16_t src_port;
439  uint16_t dst_port;
440 };
441 
445 struct rte_eth_tcpv4_flow {
446  struct rte_eth_ipv4_flow ip;
447  uint16_t src_port;
448  uint16_t dst_port;
449 };
450 
454 struct rte_eth_sctpv4_flow {
455  struct rte_eth_ipv4_flow ip;
456  uint16_t src_port;
457  uint16_t dst_port;
458  uint32_t verify_tag;
459 };
460 
464 struct rte_eth_ipv6_flow {
465  uint32_t src_ip[4];
466  uint32_t dst_ip[4];
467  uint8_t tc;
468  uint8_t proto;
469  uint8_t hop_limits;
470 };
471 
475 struct rte_eth_udpv6_flow {
476  struct rte_eth_ipv6_flow ip;
477  uint16_t src_port;
478  uint16_t dst_port;
479 };
480 
484 struct rte_eth_tcpv6_flow {
485  struct rte_eth_ipv6_flow ip;
486  uint16_t src_port;
487  uint16_t dst_port;
488 };
489 
493 struct rte_eth_sctpv6_flow {
494  struct rte_eth_ipv6_flow ip;
495  uint16_t src_port;
496  uint16_t dst_port;
497  uint32_t verify_tag;
498 };
499 
503 struct rte_eth_mac_vlan_flow {
504  struct ether_addr mac_addr;
505 };
506 
510 enum rte_eth_fdir_tunnel_type {
511  RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
512  RTE_FDIR_TUNNEL_TYPE_NVGRE,
513  RTE_FDIR_TUNNEL_TYPE_VXLAN,
514 };
515 
520 struct rte_eth_tunnel_flow {
521  enum rte_eth_fdir_tunnel_type tunnel_type;
523  uint32_t tunnel_id;
524  struct ether_addr mac_addr;
525 };
526 
531 union rte_eth_fdir_flow {
532  struct rte_eth_l2_flow l2_flow;
533  struct rte_eth_udpv4_flow udp4_flow;
534  struct rte_eth_tcpv4_flow tcp4_flow;
535  struct rte_eth_sctpv4_flow sctp4_flow;
536  struct rte_eth_ipv4_flow ip4_flow;
537  struct rte_eth_udpv6_flow udp6_flow;
538  struct rte_eth_tcpv6_flow tcp6_flow;
539  struct rte_eth_sctpv6_flow sctp6_flow;
540  struct rte_eth_ipv6_flow ipv6_flow;
541  struct rte_eth_mac_vlan_flow mac_vlan_flow;
542  struct rte_eth_tunnel_flow tunnel_flow;
543 };
544 
548 struct rte_eth_fdir_flow_ext {
549  uint16_t vlan_tci;
550  uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
552  uint8_t is_vf;
553  uint16_t dst_id;
554 };
555 
559 struct rte_eth_fdir_input {
560  uint16_t flow_type;
561  union rte_eth_fdir_flow flow;
563  struct rte_eth_fdir_flow_ext flow_ext;
565 };
566 
570 enum rte_eth_fdir_behavior {
571  RTE_ETH_FDIR_ACCEPT = 0,
572  RTE_ETH_FDIR_REJECT,
573  RTE_ETH_FDIR_PASSTHRU,
574 };
575 
580 enum rte_eth_fdir_status {
581  RTE_ETH_FDIR_NO_REPORT_STATUS = 0,
582  RTE_ETH_FDIR_REPORT_ID,
583  RTE_ETH_FDIR_REPORT_ID_FLEX_4,
584  RTE_ETH_FDIR_REPORT_FLEX_8,
585 };
586 
590 struct rte_eth_fdir_action {
591  uint16_t rx_queue;
592  enum rte_eth_fdir_behavior behavior;
593  enum rte_eth_fdir_status report_status;
594  uint8_t flex_off;
598 };
599 
605 struct rte_eth_fdir_filter {
606  uint32_t soft_id;
608  struct rte_eth_fdir_input input;
609  struct rte_eth_fdir_action action;
610 };
611 
616 struct rte_eth_fdir_masks {
617  uint16_t vlan_tci_mask;
619  struct rte_eth_ipv4_flow ipv4_mask;
621  struct rte_eth_ipv6_flow ipv6_mask;
623  uint16_t src_port_mask;
625  uint16_t dst_port_mask;
628  uint8_t mac_addr_byte_mask;
630  uint32_t tunnel_id_mask;
631  uint8_t tunnel_type_mask;
633 };
634 
638 enum rte_eth_payload_type {
639  RTE_ETH_PAYLOAD_UNKNOWN = 0,
640  RTE_ETH_RAW_PAYLOAD,
641  RTE_ETH_L2_PAYLOAD,
642  RTE_ETH_L3_PAYLOAD,
643  RTE_ETH_L4_PAYLOAD,
644  RTE_ETH_PAYLOAD_MAX = 8,
645 };
646 
651 struct rte_eth_flex_payload_cfg {
652  enum rte_eth_payload_type type;
653  uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN];
658 };
659 
664 struct rte_eth_fdir_flex_mask {
665  uint16_t flow_type;
666  uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN];
668 };
669 
674 struct rte_eth_fdir_flex_conf {
675  uint16_t nb_payloads;
676  uint16_t nb_flexmasks;
677  struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
679  struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
681 };
682 
686 enum rte_fdir_mode {
687  RTE_FDIR_MODE_NONE = 0,
688  RTE_FDIR_MODE_SIGNATURE,
689  RTE_FDIR_MODE_PERFECT,
690  RTE_FDIR_MODE_PERFECT_MAC_VLAN,
691  RTE_FDIR_MODE_PERFECT_TUNNEL,
692 };
693 
694 #define UINT32_BIT (CHAR_BIT * sizeof(uint32_t))
695 #define RTE_FLOW_MASK_ARRAY_SIZE \
696  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)
697 
705 struct rte_eth_fdir_info {
706  enum rte_fdir_mode mode;
707  struct rte_eth_fdir_masks mask;
709  struct rte_eth_fdir_flex_conf flex_conf;
710  uint32_t guarant_spc;
711  uint32_t best_spc;
713  uint32_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
714  uint32_t max_flexpayload;
717  uint32_t flex_payload_unit;
720  uint32_t max_flex_payload_segment_num;
724  uint16_t flex_payload_limit;
727  uint32_t flex_bitmask_unit;
729  uint32_t max_flex_bitmask_num;
730 };
731 
736 struct rte_eth_fdir_stats {
737  uint32_t collision;
738  uint32_t free;
739  uint32_t maxhash;
742  uint32_t maxlen;
743  uint64_t add;
744  uint64_t remove;
745  uint64_t f_add;
746  uint64_t f_remove;
747  uint32_t guarant_cnt;
748  uint32_t best_cnt;
749 };
750 
754 enum rte_eth_fdir_filter_info_type {
755  RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
757  RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT,
758  RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
759 };
760 
765 struct rte_eth_fdir_filter_info {
766  enum rte_eth_fdir_filter_info_type info_type;
768  union {
770  struct rte_eth_input_set_conf input_set_conf;
771  } info;
772 };
773 
784 enum rte_eth_hash_filter_info_type {
785  RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
787  RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT,
789  RTE_ETH_HASH_FILTER_GLOBAL_CONFIG,
791  RTE_ETH_HASH_FILTER_INPUT_SET_SELECT,
792  RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
793 };
794 
798 enum rte_eth_hash_function {
799  RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
800  RTE_ETH_HASH_FUNCTION_TOEPLITZ,
801  RTE_ETH_HASH_FUNCTION_SIMPLE_XOR,
802  RTE_ETH_HASH_FUNCTION_MAX,
803 };
804 
805 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \
806  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)
807 
816 struct rte_eth_hash_global_conf {
817  enum rte_eth_hash_function hash_func;
819  uint32_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
821  uint32_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
822 };
823 
828 struct rte_eth_hash_filter_info {
829  enum rte_eth_hash_filter_info_type info_type;
831  union {
833  uint8_t enable;
835  struct rte_eth_hash_global_conf global_conf;
837  struct rte_eth_input_set_conf input_set_conf;
838  } info;
839 };
840 
844 struct rte_eth_l2_tunnel_conf {
845  enum rte_eth_tunnel_type l2_tunnel_type;
846  uint16_t ether_type; /* ether type in l2 header */
847  uint32_t tunnel_id; /* port tag id for e-tag */
848  uint16_t vf_id; /* VF id for tag insertion */
849  uint32_t pool; /* destination pool for tag based forwarding */
850 };
851 
852 #ifdef __cplusplus
853 }
854 #endif
855 
856 #endif /* _RTE_ETH_CTRL_H_ */
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