DPDK  19.05.0
rte_tm.h
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1 /*-
2  * BSD LICENSE
3  *
4  * Copyright(c) 2017 Intel Corporation.
5  * Copyright(c) 2017 Cavium.
6  * Copyright(c) 2017 NXP.
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  *
13  * * Redistributions of source code must retain the above copyright
14  * notice, this list of conditions and the following disclaimer.
15  * * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in
17  * the documentation and/or other materials provided with the
18  * distribution.
19  * * Neither the name of Intel Corporation nor the names of its
20  * contributors may be used to endorse or promote products derived
21  * from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
28  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #ifndef __INCLUDE_RTE_TM_H__
37 #define __INCLUDE_RTE_TM_H__
38 
51 #include <stdint.h>
52 
53 #include <rte_common.h>
54 #include <rte_meter.h>
55 
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59 
73 #define RTE_TM_ETH_FRAMING_OVERHEAD 20
74 
85 #define RTE_TM_ETH_FRAMING_OVERHEAD_FCS 24
86 
94 #define RTE_TM_WRED_PROFILE_ID_NONE UINT32_MAX
95 
103 #define RTE_TM_SHAPER_PROFILE_ID_NONE UINT32_MAX
104 
110 #define RTE_TM_NODE_ID_NULL UINT32_MAX
111 
117 #define RTE_TM_NODE_LEVEL_ID_ANY UINT32_MAX
118 
122 enum rte_tm_stats_type {
124  RTE_TM_STATS_N_PKTS = 1 << 0,
125 
127  RTE_TM_STATS_N_BYTES = 1 << 1,
128 
130  RTE_TM_STATS_N_PKTS_GREEN_DROPPED = 1 << 2,
131 
133  RTE_TM_STATS_N_PKTS_YELLOW_DROPPED = 1 << 3,
134 
136  RTE_TM_STATS_N_PKTS_RED_DROPPED = 1 << 4,
137 
139  RTE_TM_STATS_N_BYTES_GREEN_DROPPED = 1 << 5,
140 
142  RTE_TM_STATS_N_BYTES_YELLOW_DROPPED = 1 << 6,
143 
145  RTE_TM_STATS_N_BYTES_RED_DROPPED = 1 << 7,
146 
150  RTE_TM_STATS_N_PKTS_QUEUED = 1 << 8,
151 
155  RTE_TM_STATS_N_BYTES_QUEUED = 1 << 9,
156 };
157 
161 struct rte_tm_node_stats {
163  uint64_t n_pkts;
164 
166  uint64_t n_bytes;
167 
169  struct {
173  uint64_t n_pkts_dropped[RTE_COLORS];
174 
178  uint64_t n_bytes_dropped[RTE_COLORS];
179 
183  uint64_t n_pkts_queued;
184 
188  uint64_t n_bytes_queued;
189  } leaf;
190 };
191 
195 enum rte_tm_dynamic_update_type {
200  RTE_TM_UPDATE_NODE_PARENT_KEEP_LEVEL = 1 << 0,
201 
206  RTE_TM_UPDATE_NODE_PARENT_CHANGE_LEVEL = 1 << 1,
207 
209  RTE_TM_UPDATE_NODE_ADD_DELETE = 1 << 2,
210 
212  RTE_TM_UPDATE_NODE_SUSPEND_RESUME = 1 << 3,
213 
215  RTE_TM_UPDATE_NODE_WFQ_WEIGHT_MODE = 1 << 4,
216 
218  RTE_TM_UPDATE_NODE_N_SP_PRIORITIES = 1 << 5,
219 
221  RTE_TM_UPDATE_NODE_CMAN = 1 << 6,
222 
224  RTE_TM_UPDATE_NODE_STATS = 1 << 7,
225 };
226 
230 struct rte_tm_capabilities {
232  uint32_t n_nodes_max;
233 
237  uint32_t n_levels_max;
238 
242  int non_leaf_nodes_identical;
243 
247  int leaf_nodes_identical;
248 
255  uint32_t shaper_n_max;
256 
261  uint32_t shaper_private_n_max;
262 
270  int shaper_private_dual_rate_n_max;
271 
275  uint64_t shaper_private_rate_min;
276 
280  uint64_t shaper_private_rate_max;
281 
285  uint32_t shaper_shared_n_max;
286 
290  uint32_t shaper_shared_n_nodes_per_shaper_max;
291 
298  uint32_t shaper_shared_n_shapers_per_node_max;
299 
304  uint32_t shaper_shared_dual_rate_n_max;
305 
309  uint64_t shaper_shared_rate_min;
310 
314  uint64_t shaper_shared_rate_max;
315 
319  int shaper_pkt_length_adjust_min;
320 
324  int shaper_pkt_length_adjust_max;
325 
331  uint32_t sched_n_children_max;
332 
341  uint32_t sched_sp_n_priorities_max;
342 
351  uint32_t sched_wfq_n_children_per_group_max;
352 
364  uint32_t sched_wfq_n_groups_max;
365 
369  uint32_t sched_wfq_weight_max;
370 
377  int cman_wred_packet_mode_supported;
378 
385  int cman_wred_byte_mode_supported;
386 
391  int cman_head_drop_supported;
392 
400  uint32_t cman_wred_context_n_max;
401 
407  uint32_t cman_wred_context_private_n_max;
408 
412  uint32_t cman_wred_context_shared_n_max;
413 
417  uint32_t cman_wred_context_shared_n_nodes_per_context_max;
418 
426  uint32_t cman_wred_context_shared_n_contexts_per_node_max;
427 
429  int mark_vlan_dei_supported[RTE_COLORS];
430 
432  int mark_ip_ecn_tcp_supported[RTE_COLORS];
433 
435  int mark_ip_ecn_sctp_supported[RTE_COLORS];
436 
438  int mark_ip_dscp_supported[RTE_COLORS];
439 
443  uint64_t dynamic_update_mask;
444 
448  uint64_t stats_mask;
449 };
450 
454 struct rte_tm_level_capabilities {
456  uint32_t n_nodes_max;
457 
462  uint32_t n_nodes_nonleaf_max;
463 
468  uint32_t n_nodes_leaf_max;
469 
474  int non_leaf_nodes_identical;
475 
480  int leaf_nodes_identical;
481 
482  RTE_STD_C11
483  union {
485  struct {
491  int shaper_private_supported;
492 
501  int shaper_private_dual_rate_supported;
502 
508  uint64_t shaper_private_rate_min;
509 
515  uint64_t shaper_private_rate_max;
516 
525  uint32_t shaper_shared_n_max;
526 
533  uint32_t sched_n_children_max;
534 
546  uint32_t sched_sp_n_priorities_max;
547 
558  uint32_t sched_wfq_n_children_per_group_max;
559 
577  uint32_t sched_wfq_n_groups_max;
578 
584  uint32_t sched_wfq_weight_max;
585 
593  uint64_t stats_mask;
594  } nonleaf;
595 
597  struct {
603  int shaper_private_supported;
604 
612  int shaper_private_dual_rate_supported;
613 
619  uint64_t shaper_private_rate_min;
620 
626  uint64_t shaper_private_rate_max;
627 
636  uint32_t shaper_shared_n_max;
637 
645  int cman_wred_packet_mode_supported;
646 
654  int cman_wred_byte_mode_supported;
655 
662  int cman_head_drop_supported;
663 
669  int cman_wred_context_private_supported;
670 
680  uint32_t cman_wred_context_shared_n_max;
681 
689  uint64_t stats_mask;
690  } leaf;
691  };
692 };
693 
697 struct rte_tm_node_capabilities {
699  int shaper_private_supported;
700 
704  int shaper_private_dual_rate_supported;
705 
710  uint64_t shaper_private_rate_min;
711 
716  uint64_t shaper_private_rate_max;
717 
722  uint32_t shaper_shared_n_max;
723 
724  RTE_STD_C11
725  union {
727  struct {
729  uint32_t sched_n_children_max;
730 
737  uint32_t sched_sp_n_priorities_max;
738 
746  uint32_t sched_wfq_n_children_per_group_max;
747 
760  uint32_t sched_wfq_n_groups_max;
761 
766  uint32_t sched_wfq_weight_max;
767  } nonleaf;
768 
770  struct {
772  int cman_wred_packet_mode_supported;
773 
775  int cman_wred_byte_mode_supported;
776 
778  int cman_head_drop_supported;
779 
781  int cman_wred_context_private_supported;
782 
788  uint32_t cman_wred_context_shared_n_max;
789  } leaf;
790  };
791 
795  uint64_t stats_mask;
796 };
797 
814 enum rte_tm_cman_mode {
815  RTE_TM_CMAN_TAIL_DROP = 0,
816  RTE_TM_CMAN_HEAD_DROP,
817  RTE_TM_CMAN_WRED,
818 };
819 
823 struct rte_tm_red_params {
825  uint64_t min_th;
826 
828  uint64_t max_th;
829 
833  uint16_t maxp_inv;
834 
836  uint16_t wq_log2;
837 };
838 
853 struct rte_tm_wred_params {
855  struct rte_tm_red_params red_params[RTE_COLORS];
856 
861  int packet_mode;
862 };
863 
867 struct rte_tm_token_bucket {
869  uint64_t rate;
870 
872  uint64_t size;
873 };
874 
893 struct rte_tm_shaper_params {
895  struct rte_tm_token_bucket committed;
896 
898  struct rte_tm_token_bucket peak;
899 
905  int32_t pkt_length_adjust;
906 };
907 
935 struct rte_tm_node_params {
940  uint32_t shaper_profile_id;
941 
943  uint32_t *shared_shaper_id;
944 
946  uint32_t n_shared_shapers;
947 
948  RTE_STD_C11
949  union {
951  struct {
958  int *wfq_weight_mode;
959 
961  uint32_t n_sp_priorities;
962  } nonleaf;
963 
965  struct {
967  enum rte_tm_cman_mode cman;
968 
972  struct {
978  uint32_t wred_profile_id;
979 
985  uint32_t *shared_wred_context_id;
986 
992  uint32_t n_shared_wred_contexts;
993  } wred;
994  } leaf;
995  };
996 
1003  uint64_t stats_mask;
1004 };
1005 
1012 enum rte_tm_error_type {
1013  RTE_TM_ERROR_TYPE_NONE,
1014  RTE_TM_ERROR_TYPE_UNSPECIFIED,
1015  RTE_TM_ERROR_TYPE_CAPABILITIES,
1016  RTE_TM_ERROR_TYPE_LEVEL_ID,
1017  RTE_TM_ERROR_TYPE_WRED_PROFILE,
1018  RTE_TM_ERROR_TYPE_WRED_PROFILE_GREEN,
1019  RTE_TM_ERROR_TYPE_WRED_PROFILE_YELLOW,
1020  RTE_TM_ERROR_TYPE_WRED_PROFILE_RED,
1021  RTE_TM_ERROR_TYPE_WRED_PROFILE_ID,
1022  RTE_TM_ERROR_TYPE_SHARED_WRED_CONTEXT_ID,
1023  RTE_TM_ERROR_TYPE_SHAPER_PROFILE,
1024  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_RATE,
1025  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_SIZE,
1026  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_RATE,
1027  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_SIZE,
1028  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PKT_ADJUST_LEN,
1029  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID,
1030  RTE_TM_ERROR_TYPE_SHARED_SHAPER_ID,
1031  RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID,
1032  RTE_TM_ERROR_TYPE_NODE_PRIORITY,
1033  RTE_TM_ERROR_TYPE_NODE_WEIGHT,
1034  RTE_TM_ERROR_TYPE_NODE_PARAMS,
1035  RTE_TM_ERROR_TYPE_NODE_PARAMS_SHAPER_PROFILE_ID,
1036  RTE_TM_ERROR_TYPE_NODE_PARAMS_SHARED_SHAPER_ID,
1037  RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SHARED_SHAPERS,
1038  RTE_TM_ERROR_TYPE_NODE_PARAMS_WFQ_WEIGHT_MODE,
1039  RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SP_PRIORITIES,
1040  RTE_TM_ERROR_TYPE_NODE_PARAMS_CMAN,
1041  RTE_TM_ERROR_TYPE_NODE_PARAMS_WRED_PROFILE_ID,
1042  RTE_TM_ERROR_TYPE_NODE_PARAMS_SHARED_WRED_CONTEXT_ID,
1043  RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SHARED_WRED_CONTEXTS,
1044  RTE_TM_ERROR_TYPE_NODE_PARAMS_STATS,
1045  RTE_TM_ERROR_TYPE_NODE_ID,
1046 };
1047 
1059 struct rte_tm_error {
1060  enum rte_tm_error_type type;
1061  const void *cause;
1062  const char *message;
1063 };
1064 
1082 int
1083 rte_tm_get_number_of_leaf_nodes(uint16_t port_id,
1084  uint32_t *n_leaf_nodes,
1085  struct rte_tm_error *error);
1086 
1106 int
1107 rte_tm_node_type_get(uint16_t port_id,
1108  uint32_t node_id,
1109  int *is_leaf,
1110  struct rte_tm_error *error);
1111 
1124 int
1125 rte_tm_capabilities_get(uint16_t port_id,
1126  struct rte_tm_capabilities *cap,
1127  struct rte_tm_error *error);
1128 
1144 int
1145 rte_tm_level_capabilities_get(uint16_t port_id,
1146  uint32_t level_id,
1147  struct rte_tm_level_capabilities *cap,
1148  struct rte_tm_error *error);
1149 
1164 int
1165 rte_tm_node_capabilities_get(uint16_t port_id,
1166  uint32_t node_id,
1167  struct rte_tm_node_capabilities *cap,
1168  struct rte_tm_error *error);
1169 
1189 int
1190 rte_tm_wred_profile_add(uint16_t port_id,
1191  uint32_t wred_profile_id,
1192  struct rte_tm_wred_params *profile,
1193  struct rte_tm_error *error);
1194 
1212 int
1213 rte_tm_wred_profile_delete(uint16_t port_id,
1214  uint32_t wred_profile_id,
1215  struct rte_tm_error *error);
1216 
1243 int
1244 rte_tm_shared_wred_context_add_update(uint16_t port_id,
1245  uint32_t shared_wred_context_id,
1246  uint32_t wred_profile_id,
1247  struct rte_tm_error *error);
1248 
1267 int
1268 rte_tm_shared_wred_context_delete(uint16_t port_id,
1269  uint32_t shared_wred_context_id,
1270  struct rte_tm_error *error);
1271 
1291 int
1292 rte_tm_shaper_profile_add(uint16_t port_id,
1293  uint32_t shaper_profile_id,
1294  struct rte_tm_shaper_params *profile,
1295  struct rte_tm_error *error);
1296 
1314 int
1315 rte_tm_shaper_profile_delete(uint16_t port_id,
1316  uint32_t shaper_profile_id,
1317  struct rte_tm_error *error);
1318 
1343 int
1344 rte_tm_shared_shaper_add_update(uint16_t port_id,
1345  uint32_t shared_shaper_id,
1346  uint32_t shaper_profile_id,
1347  struct rte_tm_error *error);
1348 
1366 int
1367 rte_tm_shared_shaper_delete(uint16_t port_id,
1368  uint32_t shared_shaper_id,
1369  struct rte_tm_error *error);
1370 
1434 int
1435 rte_tm_node_add(uint16_t port_id,
1436  uint32_t node_id,
1437  uint32_t parent_node_id,
1438  uint32_t priority,
1439  uint32_t weight,
1440  uint32_t level_id,
1441  struct rte_tm_node_params *params,
1442  struct rte_tm_error *error);
1443 
1467 int
1468 rte_tm_node_delete(uint16_t port_id,
1469  uint32_t node_id,
1470  struct rte_tm_error *error);
1471 
1491 int
1492 rte_tm_node_suspend(uint16_t port_id,
1493  uint32_t node_id,
1494  struct rte_tm_error *error);
1495 
1514 int
1515 rte_tm_node_resume(uint16_t port_id,
1516  uint32_t node_id,
1517  struct rte_tm_error *error);
1518 
1555 int
1556 rte_tm_hierarchy_commit(uint16_t port_id,
1557  int clear_on_fail,
1558  struct rte_tm_error *error);
1559 
1595 int
1596 rte_tm_node_parent_update(uint16_t port_id,
1597  uint32_t node_id,
1598  uint32_t parent_node_id,
1599  uint32_t priority,
1600  uint32_t weight,
1601  struct rte_tm_error *error);
1602 
1624 int
1625 rte_tm_node_shaper_update(uint16_t port_id,
1626  uint32_t node_id,
1627  uint32_t shaper_profile_id,
1628  struct rte_tm_error *error);
1629 
1651 int
1652 rte_tm_node_shared_shaper_update(uint16_t port_id,
1653  uint32_t node_id,
1654  uint32_t shared_shaper_id,
1655  int add,
1656  struct rte_tm_error *error);
1657 
1678 int
1679 rte_tm_node_stats_update(uint16_t port_id,
1680  uint32_t node_id,
1681  uint64_t stats_mask,
1682  struct rte_tm_error *error);
1683 
1706 int
1707 rte_tm_node_wfq_weight_mode_update(uint16_t port_id,
1708  uint32_t node_id,
1709  int *wfq_weight_mode,
1710  uint32_t n_sp_priorities,
1711  struct rte_tm_error *error);
1712 
1729 int
1730 rte_tm_node_cman_update(uint16_t port_id,
1731  uint32_t node_id,
1732  enum rte_tm_cman_mode cman,
1733  struct rte_tm_error *error);
1734 
1753 int
1754 rte_tm_node_wred_context_update(uint16_t port_id,
1755  uint32_t node_id,
1756  uint32_t wred_profile_id,
1757  struct rte_tm_error *error);
1758 
1778 int
1779 rte_tm_node_shared_wred_context_update(uint16_t port_id,
1780  uint32_t node_id,
1781  uint32_t shared_wred_context_id,
1782  int add,
1783  struct rte_tm_error *error);
1784 
1810 int
1811 rte_tm_node_stats_read(uint16_t port_id,
1812  uint32_t node_id,
1813  struct rte_tm_node_stats *stats,
1814  uint64_t *stats_mask,
1815  int clear,
1816  struct rte_tm_error *error);
1817 
1847 int
1848 rte_tm_mark_vlan_dei(uint16_t port_id,
1849  int mark_green,
1850  int mark_yellow,
1851  int mark_red,
1852  struct rte_tm_error *error);
1853 
1897 int
1898 rte_tm_mark_ip_ecn(uint16_t port_id,
1899  int mark_green,
1900  int mark_yellow,
1901  int mark_red,
1902  struct rte_tm_error *error);
1903 
1945 int
1946 rte_tm_mark_ip_dscp(uint16_t port_id,
1947  int mark_green,
1948  int mark_yellow,
1949  int mark_red,
1950  struct rte_tm_error *error);
1951 
1952 #ifdef __cplusplus
1953 }
1954 #endif
1955 
1956 #endif /* __INCLUDE_RTE_TM_H__ */
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