149 #define RTE_ETHDEV_HAS_LRO_SUPPORT
151 #include <rte_compat.h>
158 #include <rte_config.h>
161 #include "rte_dev_info.h"
163 extern int rte_eth_dev_logtype;
165 #define RTE_ETHDEV_LOG(level, ...) \
166 rte_log(RTE_LOG_ ## level, rte_eth_dev_logtype, "" __VA_ARGS__)
231 #define RTE_ETH_FOREACH_MATCHING_DEV(id, devargs, iter) \
232 for (rte_eth_iterator_init(iter, devargs), \
233 id = rte_eth_iterator_next(iter); \
234 id != RTE_MAX_ETHPORTS; \
235 id = rte_eth_iterator_next(iter))
255 uint64_t
q_ipackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];
257 uint64_t
q_opackets[RTE_ETHDEV_QUEUE_STAT_CNTRS];
259 uint64_t
q_ibytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];
261 uint64_t
q_obytes[RTE_ETHDEV_QUEUE_STAT_CNTRS];
263 uint64_t
q_errors[RTE_ETHDEV_QUEUE_STAT_CNTRS];
270 #define ETH_LINK_SPEED_AUTONEG (0 << 0)
271 #define ETH_LINK_SPEED_FIXED (1 << 0)
272 #define ETH_LINK_SPEED_10M_HD (1 << 1)
273 #define ETH_LINK_SPEED_10M (1 << 2)
274 #define ETH_LINK_SPEED_100M_HD (1 << 3)
275 #define ETH_LINK_SPEED_100M (1 << 4)
276 #define ETH_LINK_SPEED_1G (1 << 5)
277 #define ETH_LINK_SPEED_2_5G (1 << 6)
278 #define ETH_LINK_SPEED_5G (1 << 7)
279 #define ETH_LINK_SPEED_10G (1 << 8)
280 #define ETH_LINK_SPEED_20G (1 << 9)
281 #define ETH_LINK_SPEED_25G (1 << 10)
282 #define ETH_LINK_SPEED_40G (1 << 11)
283 #define ETH_LINK_SPEED_50G (1 << 12)
284 #define ETH_LINK_SPEED_56G (1 << 13)
285 #define ETH_LINK_SPEED_100G (1 << 14)
290 #define ETH_SPEED_NUM_NONE 0
291 #define ETH_SPEED_NUM_10M 10
292 #define ETH_SPEED_NUM_100M 100
293 #define ETH_SPEED_NUM_1G 1000
294 #define ETH_SPEED_NUM_2_5G 2500
295 #define ETH_SPEED_NUM_5G 5000
296 #define ETH_SPEED_NUM_10G 10000
297 #define ETH_SPEED_NUM_20G 20000
298 #define ETH_SPEED_NUM_25G 25000
299 #define ETH_SPEED_NUM_40G 40000
300 #define ETH_SPEED_NUM_50G 50000
301 #define ETH_SPEED_NUM_56G 56000
302 #define ETH_SPEED_NUM_100G 100000
313 } __attribute__((aligned(8)));
316 #define ETH_LINK_HALF_DUPLEX 0
317 #define ETH_LINK_FULL_DUPLEX 1
318 #define ETH_LINK_DOWN 0
319 #define ETH_LINK_UP 1
320 #define ETH_LINK_FIXED 0
321 #define ETH_LINK_AUTONEG 1
327 struct rte_eth_thresh {
336 #define ETH_MQ_RX_RSS_FLAG 0x1
337 #define ETH_MQ_RX_DCB_FLAG 0x2
338 #define ETH_MQ_RX_VMDQ_FLAG 0x4
369 #define ETH_RSS ETH_MQ_RX_RSS
370 #define VMDQ_DCB ETH_MQ_RX_VMDQ_DCB
371 #define ETH_DCB_RX ETH_MQ_RX_DCB
387 #define ETH_DCB_NONE ETH_MQ_TX_NONE
388 #define ETH_VMDQ_DCB_TX ETH_MQ_TX_VMDQ_DCB
389 #define ETH_DCB_TX ETH_MQ_TX_DCB
412 ETH_VLAN_TYPE_UNKNOWN = 0,
458 #define RTE_ETH_FLOW_UNKNOWN 0
459 #define RTE_ETH_FLOW_RAW 1
460 #define RTE_ETH_FLOW_IPV4 2
461 #define RTE_ETH_FLOW_FRAG_IPV4 3
462 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4
463 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5
464 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6
465 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7
466 #define RTE_ETH_FLOW_IPV6 8
467 #define RTE_ETH_FLOW_FRAG_IPV6 9
468 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10
469 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11
470 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12
471 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13
472 #define RTE_ETH_FLOW_L2_PAYLOAD 14
473 #define RTE_ETH_FLOW_IPV6_EX 15
474 #define RTE_ETH_FLOW_IPV6_TCP_EX 16
475 #define RTE_ETH_FLOW_IPV6_UDP_EX 17
476 #define RTE_ETH_FLOW_PORT 18
478 #define RTE_ETH_FLOW_VXLAN 19
479 #define RTE_ETH_FLOW_GENEVE 20
480 #define RTE_ETH_FLOW_NVGRE 21
481 #define RTE_ETH_FLOW_VXLAN_GPE 22
482 #define RTE_ETH_FLOW_MAX 23
490 #define ETH_RSS_IPV4 (1ULL << RTE_ETH_FLOW_IPV4)
491 #define ETH_RSS_FRAG_IPV4 (1ULL << RTE_ETH_FLOW_FRAG_IPV4)
492 #define ETH_RSS_NONFRAG_IPV4_TCP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP)
493 #define ETH_RSS_NONFRAG_IPV4_UDP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP)
494 #define ETH_RSS_NONFRAG_IPV4_SCTP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP)
495 #define ETH_RSS_NONFRAG_IPV4_OTHER (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER)
496 #define ETH_RSS_IPV6 (1ULL << RTE_ETH_FLOW_IPV6)
497 #define ETH_RSS_FRAG_IPV6 (1ULL << RTE_ETH_FLOW_FRAG_IPV6)
498 #define ETH_RSS_NONFRAG_IPV6_TCP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP)
499 #define ETH_RSS_NONFRAG_IPV6_UDP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP)
500 #define ETH_RSS_NONFRAG_IPV6_SCTP (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP)
501 #define ETH_RSS_NONFRAG_IPV6_OTHER (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER)
502 #define ETH_RSS_L2_PAYLOAD (1ULL << RTE_ETH_FLOW_L2_PAYLOAD)
503 #define ETH_RSS_IPV6_EX (1ULL << RTE_ETH_FLOW_IPV6_EX)
504 #define ETH_RSS_IPV6_TCP_EX (1ULL << RTE_ETH_FLOW_IPV6_TCP_EX)
505 #define ETH_RSS_IPV6_UDP_EX (1ULL << RTE_ETH_FLOW_IPV6_UDP_EX)
506 #define ETH_RSS_PORT (1ULL << RTE_ETH_FLOW_PORT)
507 #define ETH_RSS_VXLAN (1ULL << RTE_ETH_FLOW_VXLAN)
508 #define ETH_RSS_GENEVE (1ULL << RTE_ETH_FLOW_GENEVE)
509 #define ETH_RSS_NVGRE (1ULL << RTE_ETH_FLOW_NVGRE)
511 #define ETH_RSS_IP ( \
513 ETH_RSS_FRAG_IPV4 | \
514 ETH_RSS_NONFRAG_IPV4_OTHER | \
516 ETH_RSS_FRAG_IPV6 | \
517 ETH_RSS_NONFRAG_IPV6_OTHER | \
520 #define ETH_RSS_UDP ( \
521 ETH_RSS_NONFRAG_IPV4_UDP | \
522 ETH_RSS_NONFRAG_IPV6_UDP | \
525 #define ETH_RSS_TCP ( \
526 ETH_RSS_NONFRAG_IPV4_TCP | \
527 ETH_RSS_NONFRAG_IPV6_TCP | \
530 #define ETH_RSS_SCTP ( \
531 ETH_RSS_NONFRAG_IPV4_SCTP | \
532 ETH_RSS_NONFRAG_IPV6_SCTP)
534 #define ETH_RSS_TUNNEL ( \
540 #define ETH_RSS_PROTO_MASK ( \
542 ETH_RSS_FRAG_IPV4 | \
543 ETH_RSS_NONFRAG_IPV4_TCP | \
544 ETH_RSS_NONFRAG_IPV4_UDP | \
545 ETH_RSS_NONFRAG_IPV4_SCTP | \
546 ETH_RSS_NONFRAG_IPV4_OTHER | \
548 ETH_RSS_FRAG_IPV6 | \
549 ETH_RSS_NONFRAG_IPV6_TCP | \
550 ETH_RSS_NONFRAG_IPV6_UDP | \
551 ETH_RSS_NONFRAG_IPV6_SCTP | \
552 ETH_RSS_NONFRAG_IPV6_OTHER | \
553 ETH_RSS_L2_PAYLOAD | \
555 ETH_RSS_IPV6_TCP_EX | \
556 ETH_RSS_IPV6_UDP_EX | \
567 #define ETH_RSS_RETA_SIZE_64 64
568 #define ETH_RSS_RETA_SIZE_128 128
569 #define ETH_RSS_RETA_SIZE_256 256
570 #define ETH_RSS_RETA_SIZE_512 512
571 #define RTE_RETA_GROUP_SIZE 64
574 #define ETH_VMDQ_MAX_VLAN_FILTERS 64
575 #define ETH_DCB_NUM_USER_PRIORITIES 8
576 #define ETH_VMDQ_DCB_NUM_QUEUES 128
577 #define ETH_DCB_NUM_QUEUES 128
580 #define ETH_DCB_PG_SUPPORT 0x00000001
581 #define ETH_DCB_PFC_SUPPORT 0x00000002
584 #define ETH_VLAN_STRIP_OFFLOAD 0x0001
585 #define ETH_VLAN_FILTER_OFFLOAD 0x0002
586 #define ETH_VLAN_EXTEND_OFFLOAD 0x0004
589 #define ETH_VLAN_STRIP_MASK 0x0001
590 #define ETH_VLAN_FILTER_MASK 0x0002
591 #define ETH_VLAN_EXTEND_MASK 0x0004
592 #define ETH_VLAN_ID_MAX 0x0FFF
595 #define ETH_NUM_RECEIVE_MAC_ADDR 128
598 #define ETH_VMDQ_NUM_UC_HASH_ARRAY 128
601 #define ETH_VMDQ_ACCEPT_UNTAG 0x0001
602 #define ETH_VMDQ_ACCEPT_HASH_MC 0x0002
603 #define ETH_VMDQ_ACCEPT_HASH_UC 0x0004
604 #define ETH_VMDQ_ACCEPT_BROADCAST 0x0008
605 #define ETH_VMDQ_ACCEPT_MULTICAST 0x0010
608 #define ETH_MIRROR_MAX_VLANS 64
610 #define ETH_MIRROR_VIRTUAL_POOL_UP 0x01
611 #define ETH_MIRROR_UPLINK_PORT 0x02
612 #define ETH_MIRROR_DOWNLINK_PORT 0x04
613 #define ETH_MIRROR_VLAN 0x08
614 #define ETH_MIRROR_VIRTUAL_POOL_DOWN 0x10
619 struct rte_eth_vlan_mirror {
645 uint16_t
reta[RTE_RETA_GROUP_SIZE];
670 struct rte_eth_dcb_rx_conf {
676 struct rte_eth_vmdq_dcb_tx_conf {
682 struct rte_eth_dcb_tx_conf {
688 struct rte_eth_vmdq_tx_conf {
875 RTE_TUNNEL_TYPE_NONE = 0,
876 RTE_TUNNEL_TYPE_VXLAN,
877 RTE_TUNNEL_TYPE_GENEVE,
878 RTE_TUNNEL_TYPE_TEREDO,
879 RTE_TUNNEL_TYPE_NVGRE,
880 RTE_TUNNEL_TYPE_IP_IN_GRE,
881 RTE_L2_TUNNEL_TYPE_E_TAG,
882 RTE_TUNNEL_TYPE_VXLAN_GPE,
996 #define DEV_RX_OFFLOAD_VLAN_STRIP 0x00000001
997 #define DEV_RX_OFFLOAD_IPV4_CKSUM 0x00000002
998 #define DEV_RX_OFFLOAD_UDP_CKSUM 0x00000004
999 #define DEV_RX_OFFLOAD_TCP_CKSUM 0x00000008
1000 #define DEV_RX_OFFLOAD_TCP_LRO 0x00000010
1001 #define DEV_RX_OFFLOAD_QINQ_STRIP 0x00000020
1002 #define DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM 0x00000040
1003 #define DEV_RX_OFFLOAD_MACSEC_STRIP 0x00000080
1004 #define DEV_RX_OFFLOAD_HEADER_SPLIT 0x00000100
1005 #define DEV_RX_OFFLOAD_VLAN_FILTER 0x00000200
1006 #define DEV_RX_OFFLOAD_VLAN_EXTEND 0x00000400
1007 #define DEV_RX_OFFLOAD_JUMBO_FRAME 0x00000800
1008 #define DEV_RX_OFFLOAD_SCATTER 0x00002000
1009 #define DEV_RX_OFFLOAD_TIMESTAMP 0x00004000
1010 #define DEV_RX_OFFLOAD_SECURITY 0x00008000
1011 #define DEV_RX_OFFLOAD_KEEP_CRC 0x00010000
1012 #define DEV_RX_OFFLOAD_SCTP_CKSUM 0x00020000
1013 #define DEV_RX_OFFLOAD_OUTER_UDP_CKSUM 0x00040000
1015 #define DEV_RX_OFFLOAD_CHECKSUM (DEV_RX_OFFLOAD_IPV4_CKSUM | \
1016 DEV_RX_OFFLOAD_UDP_CKSUM | \
1017 DEV_RX_OFFLOAD_TCP_CKSUM)
1018 #define DEV_RX_OFFLOAD_VLAN (DEV_RX_OFFLOAD_VLAN_STRIP | \
1019 DEV_RX_OFFLOAD_VLAN_FILTER | \
1020 DEV_RX_OFFLOAD_VLAN_EXTEND)
1030 #define DEV_TX_OFFLOAD_VLAN_INSERT 0x00000001
1031 #define DEV_TX_OFFLOAD_IPV4_CKSUM 0x00000002
1032 #define DEV_TX_OFFLOAD_UDP_CKSUM 0x00000004
1033 #define DEV_TX_OFFLOAD_TCP_CKSUM 0x00000008
1034 #define DEV_TX_OFFLOAD_SCTP_CKSUM 0x00000010
1035 #define DEV_TX_OFFLOAD_TCP_TSO 0x00000020
1036 #define DEV_TX_OFFLOAD_UDP_TSO 0x00000040
1037 #define DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM 0x00000080
1038 #define DEV_TX_OFFLOAD_QINQ_INSERT 0x00000100
1039 #define DEV_TX_OFFLOAD_VXLAN_TNL_TSO 0x00000200
1040 #define DEV_TX_OFFLOAD_GRE_TNL_TSO 0x00000400
1041 #define DEV_TX_OFFLOAD_IPIP_TNL_TSO 0x00000800
1042 #define DEV_TX_OFFLOAD_GENEVE_TNL_TSO 0x00001000
1043 #define DEV_TX_OFFLOAD_MACSEC_INSERT 0x00002000
1044 #define DEV_TX_OFFLOAD_MT_LOCKFREE 0x00004000
1048 #define DEV_TX_OFFLOAD_MULTI_SEGS 0x00008000
1050 #define DEV_TX_OFFLOAD_MBUF_FAST_FREE 0x00010000
1055 #define DEV_TX_OFFLOAD_SECURITY 0x00020000
1061 #define DEV_TX_OFFLOAD_UDP_TNL_TSO 0x00040000
1067 #define DEV_TX_OFFLOAD_IP_TNL_TSO 0x00080000
1069 #define DEV_TX_OFFLOAD_OUTER_UDP_CKSUM 0x00100000
1074 #define DEV_TX_OFFLOAD_MATCH_METADATA 0x00200000
1076 #define RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP 0x00000001
1078 #define RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP 0x00000002
1091 #define RTE_ETH_DEV_FALLBACK_RX_RINGSIZE 512
1092 #define RTE_ETH_DEV_FALLBACK_TX_RINGSIZE 512
1093 #define RTE_ETH_DEV_FALLBACK_RX_NBQUEUES 1
1094 #define RTE_ETH_DEV_FALLBACK_TX_NBQUEUES 1
1111 #define RTE_ETH_DEV_SWITCH_DOMAIN_ID_INVALID (0)
1151 uint32_t max_hash_mac_addrs;
1213 #define RTE_ETH_XSTATS_NAME_SIZE 64
1240 #define ETH_DCB_NUM_TCS 8
1241 #define ETH_MAX_VMDQ_POOL 64
1252 }
tc_rxq[ETH_MAX_VMDQ_POOL][ETH_DCB_NUM_TCS];
1257 }
tc_txq[ETH_MAX_VMDQ_POOL][ETH_DCB_NUM_TCS];
1275 #define RTE_ETH_QUEUE_STATE_STOPPED 0
1276 #define RTE_ETH_QUEUE_STATE_STARTED 1
1278 #define RTE_ETH_ALL RTE_MAX_ETHPORTS
1281 #define RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, retval) do { \
1282 if (!rte_eth_dev_is_valid_port(port_id)) { \
1283 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%u\n", port_id); \
1288 #define RTE_ETH_VALID_PORTID_OR_RET(port_id) do { \
1289 if (!rte_eth_dev_is_valid_port(port_id)) { \
1290 RTE_ETHDEV_LOG(ERR, "Invalid port_id=%u\n", port_id); \
1300 #define ETH_L2_TUNNEL_ENABLE_MASK 0x00000001
1302 #define ETH_L2_TUNNEL_INSERTION_MASK 0x00000002
1304 #define ETH_L2_TUNNEL_STRIPPING_MASK 0x00000004
1306 #define ETH_L2_TUNNEL_FORWARDING_MASK 0x00000008
1331 struct rte_mbuf *pkts[], uint16_t nb_pkts, uint16_t max_pkts,
1355 struct rte_mbuf *pkts[], uint16_t nb_pkts,
void *user_param);
1369 struct rte_eth_dev_sriov {
1371 uint8_t nb_q_per_pool;
1372 uint16_t def_vmdq_idx;
1373 uint16_t def_pool_q_idx;
1375 #define RTE_ETH_DEV_SRIOV(dev) ((dev)->data->sriov)
1377 #define RTE_ETH_NAME_MAX_LEN RTE_DEV_NAME_MAX_LEN
1379 #define RTE_ETH_DEV_NO_OWNER 0
1381 #define RTE_ETH_MAX_OWNER_NAME_LEN 64
1383 struct rte_eth_dev_owner {
1385 char name[RTE_ETH_MAX_OWNER_NAME_LEN];
1392 #define RTE_ETH_DEV_CLOSE_REMOVE 0x0001
1394 #define RTE_ETH_DEV_INTR_LSC 0x0002
1396 #define RTE_ETH_DEV_BONDED_SLAVE 0x0004
1398 #define RTE_ETH_DEV_INTR_RMV 0x0008
1400 #define RTE_ETH_DEV_REPRESENTOR 0x0010
1402 #define RTE_ETH_DEV_NOLIVE_MAC_ADDR 0x0020
1416 const uint64_t owner_id);
1421 #define RTE_ETH_FOREACH_DEV_OWNED_BY(p, o) \
1422 for (p = rte_eth_find_next_owned_by(0, o); \
1423 (unsigned int)p < (unsigned int)RTE_MAX_ETHPORTS; \
1424 p = rte_eth_find_next_owned_by(p + 1, o))
1439 #define RTE_ETH_FOREACH_DEV(p) \
1440 RTE_ETH_FOREACH_DEV_OWNED_BY(p, RTE_ETH_DEV_NO_OWNER)
1456 uint16_t __rte_experimental
1468 #define RTE_ETH_FOREACH_DEV_OF(port_id, parent) \
1469 for (port_id = rte_eth_find_next_of(0, parent); \
1470 port_id < RTE_MAX_ETHPORTS; \
1471 port_id = rte_eth_find_next_of(port_id + 1, parent))
1487 uint16_t __rte_experimental
1489 uint16_t ref_port_id);
1501 #define RTE_ETH_FOREACH_DEV_SIBLING(port_id, ref_port_id) \
1502 for (port_id = rte_eth_find_next_sibling(0, ref_port_id); \
1503 port_id < RTE_MAX_ETHPORTS; \
1504 port_id = rte_eth_find_next_sibling(port_id + 1, ref_port_id))
1535 const struct rte_eth_dev_owner *owner);
1551 const uint64_t owner_id);
1578 struct rte_eth_dev_owner *owner);
1690 uint16_t nb_tx_queue,
const struct rte_eth_conf *eth_conf);
1703 int __rte_experimental
1756 uint16_t nb_rx_desc,
unsigned int socket_id,
1809 uint16_t nb_tx_desc,
unsigned int socket_id,
2238 uint64_t *values,
unsigned int size);
2287 uint16_t tx_queue_id, uint8_t stat_idx);
2307 uint16_t rx_queue_id,
2379 char *fw_version,
size_t fw_size);
2420 uint32_t *ptypes,
int num);
2571 typedef void (*buffer_tx_error_fn)(
struct rte_mbuf **unsent, uint16_t count,
2579 buffer_tx_error_fn error_callback;
2580 void *error_userdata;
2593 #define RTE_ETH_TX_BUFFER_SIZE(sz) \
2594 (sizeof(struct rte_eth_dev_tx_buffer) + (sz) * sizeof(struct rte_mbuf *))
2635 buffer_tx_error_fn callback,
void *
userdata);
2910 int epfd,
int op,
void *data);
2929 int __rte_experimental
3084 uint16_t reta_size);
3105 uint16_t reta_size);
3349 struct rte_eth_rxtx_callback;
3375 const struct rte_eth_rxtx_callback *
3404 const struct rte_eth_rxtx_callback *
3432 const struct rte_eth_rxtx_callback *
3467 const struct rte_eth_rxtx_callback *user_cb);
3500 const struct rte_eth_rxtx_callback *user_cb);
3626 int __rte_experimental
3648 int __rte_experimental
3650 struct rte_dev_eeprom_info *info);
3672 uint32_t nb_mc_addr);
3721 struct timespec *timestamp, uint32_t flags);
3739 struct timespec *timestamp);
3897 uint16_t *nb_rx_desc,
3898 uint16_t *nb_tx_desc);
4014 static inline uint16_t
4016 struct rte_mbuf **rx_pkts,
const uint16_t nb_pkts)
4018 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4021 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4022 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
4023 RTE_FUNC_PTR_OR_ERR_RET(*dev->rx_pkt_burst, 0);
4025 if (queue_id >= dev->data->nb_rx_queues) {
4026 RTE_ETHDEV_LOG(ERR,
"Invalid RX queue_id=%u\n", queue_id);
4030 nb_rx = (*dev->rx_pkt_burst)(dev->data->rx_queues[queue_id],
4033 #ifdef RTE_ETHDEV_RXTX_CALLBACKS
4034 if (
unlikely(dev->post_rx_burst_cbs[queue_id] != NULL)) {
4035 struct rte_eth_rxtx_callback *cb =
4036 dev->post_rx_burst_cbs[queue_id];
4039 nb_rx = cb->fn.rx(port_id, queue_id, rx_pkts, nb_rx,
4040 nb_pkts, cb->param);
4042 }
while (cb != NULL);
4064 struct rte_eth_dev *dev;
4066 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
4067 dev = &rte_eth_devices[port_id];
4068 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_queue_count, -ENOTSUP);
4069 if (queue_id >= dev->data->nb_rx_queues)
4072 return (
int)(*dev->dev_ops->rx_queue_count)(dev, queue_id);
4093 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4094 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4095 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_descriptor_done, -ENOTSUP);
4096 return (*dev->dev_ops->rx_descriptor_done)( \
4097 dev->data->rx_queues[queue_id], offset);
4100 #define RTE_ETH_RX_DESC_AVAIL 0
4101 #define RTE_ETH_RX_DESC_DONE 1
4102 #define RTE_ETH_RX_DESC_UNAVAIL 2
4141 struct rte_eth_dev *dev;
4144 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4145 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4147 dev = &rte_eth_devices[port_id];
4148 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4149 if (queue_id >= dev->data->nb_rx_queues)
4152 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->rx_descriptor_status, -ENOTSUP);
4153 rxq = dev->data->rx_queues[queue_id];
4155 return (*dev->dev_ops->rx_descriptor_status)(rxq, offset);
4158 #define RTE_ETH_TX_DESC_FULL 0
4159 #define RTE_ETH_TX_DESC_DONE 1
4160 #define RTE_ETH_TX_DESC_UNAVAIL 2
4195 static inline int rte_eth_tx_descriptor_status(uint16_t port_id,
4196 uint16_t queue_id, uint16_t offset)
4198 struct rte_eth_dev *dev;
4201 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4202 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -ENODEV);
4204 dev = &rte_eth_devices[port_id];
4205 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4206 if (queue_id >= dev->data->nb_tx_queues)
4209 RTE_FUNC_PTR_OR_ERR_RET(*dev->dev_ops->tx_descriptor_status, -ENOTSUP);
4210 txq = dev->data->tx_queues[queue_id];
4212 return (*dev->dev_ops->tx_descriptor_status)(txq, offset);
4281 static inline uint16_t
4283 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
4285 struct rte_eth_dev *dev = &rte_eth_devices[port_id];
4287 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4288 RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, 0);
4289 RTE_FUNC_PTR_OR_ERR_RET(*dev->tx_pkt_burst, 0);
4291 if (queue_id >= dev->data->nb_tx_queues) {
4292 RTE_ETHDEV_LOG(ERR,
"Invalid TX queue_id=%u\n", queue_id);
4297 #ifdef RTE_ETHDEV_RXTX_CALLBACKS
4298 struct rte_eth_rxtx_callback *cb = dev->pre_tx_burst_cbs[queue_id];
4302 nb_pkts = cb->fn.tx(port_id, queue_id, tx_pkts, nb_pkts,
4305 }
while (cb != NULL);
4309 return (*dev->tx_pkt_burst)(dev->data->tx_queues[queue_id], tx_pkts, nb_pkts);
4365 #ifndef RTE_ETHDEV_TX_PREPARE_NOOP
4367 static inline uint16_t
4369 struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
4371 struct rte_eth_dev *dev;
4373 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4375 RTE_ETHDEV_LOG(ERR,
"Invalid TX port_id=%u\n", port_id);
4381 dev = &rte_eth_devices[port_id];
4383 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
4384 if (queue_id >= dev->data->nb_tx_queues) {
4385 RTE_ETHDEV_LOG(ERR,
"Invalid TX queue_id=%u\n", queue_id);
4391 if (!dev->tx_pkt_prepare)
4394 return (*dev->tx_pkt_prepare)(dev->data->tx_queues[queue_id],
4409 static inline uint16_t
4441 static inline uint16_t
4446 uint16_t to_send = buffer->
length;
4457 buffer->error_callback(&buffer->
pkts[sent],
4458 (uint16_t)(to_send - sent),
4459 buffer->error_userdata);