DPDK  19.05.0
rte_eth_ctrl.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2015 Intel Corporation
3  */
4 
5 #ifndef _RTE_ETH_CTRL_H_
6 #define _RTE_ETH_CTRL_H_
7 
8 #include <stdint.h>
9 #include <rte_common.h>
10 #include "rte_ether.h"
11 #include "rte_flow.h"
12 
21 #ifdef __cplusplus
22 extern "C" {
23 #endif
24 
28 enum rte_filter_type {
29  RTE_ETH_FILTER_NONE = 0,
30  RTE_ETH_FILTER_MACVLAN,
31  RTE_ETH_FILTER_ETHERTYPE,
32  RTE_ETH_FILTER_FLEXIBLE,
33  RTE_ETH_FILTER_SYN,
34  RTE_ETH_FILTER_NTUPLE,
35  RTE_ETH_FILTER_TUNNEL,
36  RTE_ETH_FILTER_FDIR,
37  RTE_ETH_FILTER_HASH,
38  RTE_ETH_FILTER_L2_TUNNEL,
39  RTE_ETH_FILTER_GENERIC,
40  RTE_ETH_FILTER_MAX
41 };
42 
46 enum rte_filter_op {
48  RTE_ETH_FILTER_NOP = 0,
49  RTE_ETH_FILTER_ADD,
50  RTE_ETH_FILTER_UPDATE,
51  RTE_ETH_FILTER_DELETE,
52  RTE_ETH_FILTER_FLUSH,
53  RTE_ETH_FILTER_GET,
54  RTE_ETH_FILTER_SET,
55  RTE_ETH_FILTER_INFO,
56  RTE_ETH_FILTER_STATS,
57  RTE_ETH_FILTER_OP_MAX
58 };
59 
63 enum rte_mac_filter_type {
64  RTE_MAC_PERFECT_MATCH = 1,
65  RTE_MACVLAN_PERFECT_MATCH,
66  RTE_MAC_HASH_MATCH,
68  RTE_MACVLAN_HASH_MATCH,
69 };
70 
74 struct rte_eth_mac_filter {
75  uint8_t is_vf;
76  uint16_t dst_id;
77  enum rte_mac_filter_type filter_type;
78  struct ether_addr mac_addr;
79 };
80 
85 #define RTE_ETHTYPE_FLAGS_MAC 0x0001
86 #define RTE_ETHTYPE_FLAGS_DROP 0x0002
93 struct rte_eth_ethertype_filter {
94  struct ether_addr mac_addr;
95  uint16_t ether_type;
96  uint16_t flags;
97  uint16_t queue;
98 };
99 
100 #define RTE_FLEX_FILTER_MAXLEN 128
101 #define RTE_FLEX_FILTER_MASK_SIZE \
102  (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
103 
110 struct rte_eth_flex_filter {
111  uint16_t len;
112  uint8_t bytes[RTE_FLEX_FILTER_MAXLEN];
113  uint8_t mask[RTE_FLEX_FILTER_MASK_SIZE];
115  uint8_t priority;
116  uint16_t queue;
117 };
118 
124 struct rte_eth_syn_filter {
125  uint8_t hig_pri;
127  uint16_t queue;
128 };
129 
134 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
135 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
136 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
137 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
138 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
139 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
141 #define RTE_5TUPLE_FLAGS ( \
142  RTE_NTUPLE_FLAGS_DST_IP | \
143  RTE_NTUPLE_FLAGS_SRC_IP | \
144  RTE_NTUPLE_FLAGS_DST_PORT | \
145  RTE_NTUPLE_FLAGS_SRC_PORT | \
146  RTE_NTUPLE_FLAGS_PROTO)
147 
148 #define RTE_2TUPLE_FLAGS ( \
149  RTE_NTUPLE_FLAGS_DST_PORT | \
150  RTE_NTUPLE_FLAGS_PROTO)
151 
152 #define TCP_URG_FLAG 0x20
153 #define TCP_ACK_FLAG 0x10
154 #define TCP_PSH_FLAG 0x08
155 #define TCP_RST_FLAG 0x04
156 #define TCP_SYN_FLAG 0x02
157 #define TCP_FIN_FLAG 0x01
158 #define TCP_FLAG_ALL 0x3F
159 
165 struct rte_eth_ntuple_filter {
166  uint16_t flags;
167  uint32_t dst_ip;
168  uint32_t dst_ip_mask;
169  uint32_t src_ip;
170  uint32_t src_ip_mask;
171  uint16_t dst_port;
172  uint16_t dst_port_mask;
173  uint16_t src_port;
174  uint16_t src_port_mask;
175  uint8_t proto;
176  uint8_t proto_mask;
180  uint8_t tcp_flags;
181  uint16_t priority;
183  uint16_t queue;
184 };
185 
189 #define ETH_TUNNEL_FILTER_OMAC 0x01
190 #define ETH_TUNNEL_FILTER_OIP 0x02
191 #define ETH_TUNNEL_FILTER_TENID 0x04
192 #define ETH_TUNNEL_FILTER_IMAC 0x08
193 #define ETH_TUNNEL_FILTER_IVLAN 0x10
194 #define ETH_TUNNEL_FILTER_IIP 0x20
196 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
197  ETH_TUNNEL_FILTER_IVLAN)
198 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
199  ETH_TUNNEL_FILTER_IVLAN | \
200  ETH_TUNNEL_FILTER_TENID)
201 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
202  ETH_TUNNEL_FILTER_TENID)
203 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
204  ETH_TUNNEL_FILTER_TENID | \
205  ETH_TUNNEL_FILTER_IMAC)
206 
210 enum rte_tunnel_iptype {
211  RTE_TUNNEL_IPTYPE_IPV4 = 0,
212  RTE_TUNNEL_IPTYPE_IPV6,
213 };
214 
218 struct rte_eth_tunnel_filter_conf {
219  struct ether_addr outer_mac;
220  struct ether_addr inner_mac;
221  uint16_t inner_vlan;
222  enum rte_tunnel_iptype ip_type;
226  union {
227  uint32_t ipv4_addr;
228  uint32_t ipv6_addr[4];
229  } ip_addr;
231  uint16_t filter_type;
232  enum rte_eth_tunnel_type tunnel_type;
233  uint32_t tenant_id;
234  uint16_t queue_id;
235 };
236 
240 enum rte_eth_global_cfg_type {
241  RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
242  RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
243  RTE_ETH_GLOBAL_CFG_TYPE_MAX,
244 };
245 
249 struct rte_eth_global_cfg {
250  enum rte_eth_global_cfg_type cfg_type;
251  union {
252  uint8_t gre_key_len;
253  uint64_t reserved;
254  } cfg;
255 };
256 
257 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
258 #define RTE_ETH_INSET_SIZE_MAX 128
263 enum rte_eth_input_set_field {
264  RTE_ETH_INPUT_SET_UNKNOWN = 0,
265 
266  /* L2 */
267  RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
268  RTE_ETH_INPUT_SET_L2_DST_MAC,
269  RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
270  RTE_ETH_INPUT_SET_L2_INNER_VLAN,
271  RTE_ETH_INPUT_SET_L2_ETHERTYPE,
272 
273  /* L3 */
274  RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
275  RTE_ETH_INPUT_SET_L3_DST_IP4,
276  RTE_ETH_INPUT_SET_L3_SRC_IP6,
277  RTE_ETH_INPUT_SET_L3_DST_IP6,
278  RTE_ETH_INPUT_SET_L3_IP4_TOS,
279  RTE_ETH_INPUT_SET_L3_IP4_PROTO,
280  RTE_ETH_INPUT_SET_L3_IP6_TC,
281  RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
282  RTE_ETH_INPUT_SET_L3_IP4_TTL,
283  RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
284 
285  /* L4 */
286  RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
287  RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
288  RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
289  RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
290  RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
291  RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
292  RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
293 
294  /* Tunnel */
295  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
296  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
297  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
298  RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
299  RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
300 
301  /* Flexible Payload */
302  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
303  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
304  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
305  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
306  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
307  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
308  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
309  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
310 
311  RTE_ETH_INPUT_SET_DEFAULT = 65533,
312  RTE_ETH_INPUT_SET_NONE = 65534,
313  RTE_ETH_INPUT_SET_MAX = 65535,
314 };
315 
319 enum rte_filter_input_set_op {
320  RTE_ETH_INPUT_SET_OP_UNKNOWN,
321  RTE_ETH_INPUT_SET_SELECT,
322  RTE_ETH_INPUT_SET_ADD,
323  RTE_ETH_INPUT_SET_OP_MAX
324 };
325 
326 
331 struct rte_eth_input_set_conf {
332  uint16_t flow_type;
333  uint16_t inset_size;
334  enum rte_eth_input_set_field field[RTE_ETH_INSET_SIZE_MAX];
335  enum rte_filter_input_set_op op;
336 };
337 
341 struct rte_eth_l2_flow {
342  uint16_t ether_type;
343 };
344 
348 struct rte_eth_ipv4_flow {
349  uint32_t src_ip;
350  uint32_t dst_ip;
351  uint8_t tos;
352  uint8_t ttl;
353  uint8_t proto;
354 };
355 
359 struct rte_eth_udpv4_flow {
360  struct rte_eth_ipv4_flow ip;
361  uint16_t src_port;
362  uint16_t dst_port;
363 };
364 
368 struct rte_eth_tcpv4_flow {
369  struct rte_eth_ipv4_flow ip;
370  uint16_t src_port;
371  uint16_t dst_port;
372 };
373 
377 struct rte_eth_sctpv4_flow {
378  struct rte_eth_ipv4_flow ip;
379  uint16_t src_port;
380  uint16_t dst_port;
381  uint32_t verify_tag;
382 };
383 
387 struct rte_eth_ipv6_flow {
388  uint32_t src_ip[4];
389  uint32_t dst_ip[4];
390  uint8_t tc;
391  uint8_t proto;
392  uint8_t hop_limits;
393 };
394 
398 struct rte_eth_udpv6_flow {
399  struct rte_eth_ipv6_flow ip;
400  uint16_t src_port;
401  uint16_t dst_port;
402 };
403 
407 struct rte_eth_tcpv6_flow {
408  struct rte_eth_ipv6_flow ip;
409  uint16_t src_port;
410  uint16_t dst_port;
411 };
412 
416 struct rte_eth_sctpv6_flow {
417  struct rte_eth_ipv6_flow ip;
418  uint16_t src_port;
419  uint16_t dst_port;
420  uint32_t verify_tag;
421 };
422 
426 struct rte_eth_mac_vlan_flow {
427  struct ether_addr mac_addr;
428 };
429 
433 enum rte_eth_fdir_tunnel_type {
434  RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
435  RTE_FDIR_TUNNEL_TYPE_NVGRE,
436  RTE_FDIR_TUNNEL_TYPE_VXLAN,
437 };
438 
443 struct rte_eth_tunnel_flow {
444  enum rte_eth_fdir_tunnel_type tunnel_type;
446  uint32_t tunnel_id;
447  struct ether_addr mac_addr;
448 };
449 
454 union rte_eth_fdir_flow {
455  struct rte_eth_l2_flow l2_flow;
456  struct rte_eth_udpv4_flow udp4_flow;
457  struct rte_eth_tcpv4_flow tcp4_flow;
458  struct rte_eth_sctpv4_flow sctp4_flow;
459  struct rte_eth_ipv4_flow ip4_flow;
460  struct rte_eth_udpv6_flow udp6_flow;
461  struct rte_eth_tcpv6_flow tcp6_flow;
462  struct rte_eth_sctpv6_flow sctp6_flow;
463  struct rte_eth_ipv6_flow ipv6_flow;
464  struct rte_eth_mac_vlan_flow mac_vlan_flow;
465  struct rte_eth_tunnel_flow tunnel_flow;
466 };
467 
471 struct rte_eth_fdir_flow_ext {
472  uint16_t vlan_tci;
473  uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
475  uint8_t is_vf;
476  uint16_t dst_id;
477 };
478 
482 struct rte_eth_fdir_input {
483  uint16_t flow_type;
484  union rte_eth_fdir_flow flow;
486  struct rte_eth_fdir_flow_ext flow_ext;
488 };
489 
493 enum rte_eth_fdir_behavior {
494  RTE_ETH_FDIR_ACCEPT = 0,
495  RTE_ETH_FDIR_REJECT,
496  RTE_ETH_FDIR_PASSTHRU,
497 };
498 
503 enum rte_eth_fdir_status {
504  RTE_ETH_FDIR_NO_REPORT_STATUS = 0,
505  RTE_ETH_FDIR_REPORT_ID,
506  RTE_ETH_FDIR_REPORT_ID_FLEX_4,
507  RTE_ETH_FDIR_REPORT_FLEX_8,
508 };
509 
513 struct rte_eth_fdir_action {
514  uint16_t rx_queue;
515  enum rte_eth_fdir_behavior behavior;
516  enum rte_eth_fdir_status report_status;
517  uint8_t flex_off;
521 };
522 
528 struct rte_eth_fdir_filter {
529  uint32_t soft_id;
531  struct rte_eth_fdir_input input;
532  struct rte_eth_fdir_action action;
533 };
534 
539 struct rte_eth_fdir_masks {
540  uint16_t vlan_tci_mask;
542  struct rte_eth_ipv4_flow ipv4_mask;
544  struct rte_eth_ipv6_flow ipv6_mask;
546  uint16_t src_port_mask;
548  uint16_t dst_port_mask;
551  uint8_t mac_addr_byte_mask;
553  uint32_t tunnel_id_mask;
554  uint8_t tunnel_type_mask;
556 };
557 
561 enum rte_eth_payload_type {
562  RTE_ETH_PAYLOAD_UNKNOWN = 0,
563  RTE_ETH_RAW_PAYLOAD,
564  RTE_ETH_L2_PAYLOAD,
565  RTE_ETH_L3_PAYLOAD,
566  RTE_ETH_L4_PAYLOAD,
567  RTE_ETH_PAYLOAD_MAX = 8,
568 };
569 
574 struct rte_eth_flex_payload_cfg {
575  enum rte_eth_payload_type type;
576  uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN];
581 };
582 
587 struct rte_eth_fdir_flex_mask {
588  uint16_t flow_type;
589  uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN];
591 };
592 
597 struct rte_eth_fdir_flex_conf {
598  uint16_t nb_payloads;
599  uint16_t nb_flexmasks;
600  struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
602  struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
604 };
605 
609 enum rte_fdir_mode {
610  RTE_FDIR_MODE_NONE = 0,
611  RTE_FDIR_MODE_SIGNATURE,
612  RTE_FDIR_MODE_PERFECT,
613  RTE_FDIR_MODE_PERFECT_MAC_VLAN,
614  RTE_FDIR_MODE_PERFECT_TUNNEL,
615 };
616 
617 #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
618 #define RTE_FLOW_MASK_ARRAY_SIZE \
619  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
620 
628 struct rte_eth_fdir_info {
629  enum rte_fdir_mode mode;
630  struct rte_eth_fdir_masks mask;
632  struct rte_eth_fdir_flex_conf flex_conf;
633  uint32_t guarant_spc;
634  uint32_t best_spc;
636  uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
637  uint32_t max_flexpayload;
640  uint32_t flex_payload_unit;
643  uint32_t max_flex_payload_segment_num;
647  uint16_t flex_payload_limit;
650  uint32_t flex_bitmask_unit;
652  uint32_t max_flex_bitmask_num;
653 };
654 
659 struct rte_eth_fdir_stats {
660  uint32_t collision;
661  uint32_t free;
662  uint32_t maxhash;
665  uint32_t maxlen;
666  uint64_t add;
667  uint64_t remove;
668  uint64_t f_add;
669  uint64_t f_remove;
670  uint32_t guarant_cnt;
671  uint32_t best_cnt;
672 };
673 
677 enum rte_eth_fdir_filter_info_type {
678  RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
680  RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT,
681  RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
682 };
683 
688 struct rte_eth_fdir_filter_info {
689  enum rte_eth_fdir_filter_info_type info_type;
691  union {
693  struct rte_eth_input_set_conf input_set_conf;
694  } info;
695 };
696 
707 enum rte_eth_hash_filter_info_type {
708  RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
710  RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT,
712  RTE_ETH_HASH_FILTER_GLOBAL_CONFIG,
714  RTE_ETH_HASH_FILTER_INPUT_SET_SELECT,
715  RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
716 };
717 
718 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \
719  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
720 
729 struct rte_eth_hash_global_conf {
730  enum rte_eth_hash_function hash_func;
732  uint64_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
734  uint64_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
735 };
736 
741 struct rte_eth_hash_filter_info {
742  enum rte_eth_hash_filter_info_type info_type;
744  union {
746  uint8_t enable;
748  struct rte_eth_hash_global_conf global_conf;
750  struct rte_eth_input_set_conf input_set_conf;
751  } info;
752 };
753 
757 struct rte_eth_l2_tunnel_conf {
758  enum rte_eth_tunnel_type l2_tunnel_type;
759  uint16_t ether_type; /* ether type in l2 header */
760  uint32_t tunnel_id; /* port tag id for e-tag */
761  uint16_t vf_id; /* VF id for tag insertion */
762  uint32_t pool; /* destination pool for tag based forwarding */
763 };
764 
765 #ifdef __cplusplus
766 }
767 #endif
768 
769 #endif /* _RTE_ETH_CTRL_H_ */
Generated by   doxygen 1.8.1.2