23 #include <rte_compat.h>
24 #include <rte_config.h>
31 RTE_PGSIZE_4K = 1ULL << 12,
32 RTE_PGSIZE_64K = 1ULL << 16,
33 RTE_PGSIZE_256K = 1ULL << 18,
34 RTE_PGSIZE_2M = 1ULL << 21,
35 RTE_PGSIZE_16M = 1ULL << 24,
36 RTE_PGSIZE_256M = 1ULL << 28,
37 RTE_PGSIZE_512M = 1ULL << 29,
38 RTE_PGSIZE_1G = 1ULL << 30,
39 RTE_PGSIZE_4G = 1ULL << 32,
40 RTE_PGSIZE_16G = 1ULL << 34,
43 #define SOCKET_ID_ANY -1
44 #define RTE_CACHE_LINE_MASK (RTE_CACHE_LINE_SIZE-1)
46 #define RTE_CACHE_LINE_ROUNDUP(size) \
47 (RTE_CACHE_LINE_SIZE * ((size + RTE_CACHE_LINE_SIZE - 1) / RTE_CACHE_LINE_SIZE))
51 #if RTE_CACHE_LINE_SIZE == 64
52 #define RTE_CACHE_LINE_SIZE_LOG2 6
53 #elif RTE_CACHE_LINE_SIZE == 128
54 #define RTE_CACHE_LINE_SIZE_LOG2 7
56 #error "Unsupported cache line size"
59 #define RTE_CACHE_LINE_MIN_SIZE 64
64 #define __rte_cache_aligned __rte_aligned(RTE_CACHE_LINE_SIZE)
69 #define __rte_cache_min_aligned __rte_aligned(RTE_CACHE_LINE_MIN_SIZE)
72 #define RTE_BAD_PHYS_ADDR ((phys_addr_t)-1)
81 #define RTE_BAD_IOVA ((rte_iova_t)-1)
86 #define RTE_MEMSEG_FLAG_DO_NOT_FREE (1 << 0)
91 phys_addr_t phys_addr;
100 uint64_t hugepage_sz;
151 __rte_experimental
void *
165 __rte_experimental
struct rte_memseg *
187 const struct rte_memseg *ms,
void *arg);
199 const struct rte_memseg *ms,
size_t len,
void *arg);
230 int __rte_experimental
251 int __rte_experimental
272 int __rte_experimental
290 int __rte_experimental
308 int __rte_experimental
326 int __rte_experimental
350 int __rte_experimental
374 int __rte_experimental
398 int __rte_experimental
422 int __rte_experimental
463 int __rte_experimental
465 unsigned int n_pages,
size_t page_sz);
493 int __rte_experimental
519 int __rte_experimental
545 int __rte_experimental
648 #define RTE_MEM_EVENT_CALLBACK_NAME_LEN 64
655 const void *addr,
size_t len,
void *arg);
682 int __rte_experimental
700 int __rte_experimental
704 #define RTE_MEM_ALLOC_VALIDATOR_NAME_LEN 64
713 size_t cur_limit,
size_t new_len);
749 int __rte_experimental
767 int __rte_experimental