DPDK  18.05.1
rte_pmd_ixgbe.h
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1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2016 Intel Corporation
3  */
4 
11 #ifndef _PMD_IXGBE_H_
12 #define _PMD_IXGBE_H_
13 
14 #include <rte_ethdev_driver.h>
15 
28 int rte_pmd_ixgbe_ping_vf(uint16_t port, uint16_t vf);
29 
44 int rte_pmd_ixgbe_set_vf_mac_addr(uint16_t port, uint16_t vf,
45  struct ether_addr *mac_addr);
46 
62 int rte_pmd_ixgbe_set_vf_vlan_anti_spoof(uint16_t port, uint16_t vf,
63  uint8_t on);
64 
80 int rte_pmd_ixgbe_set_vf_mac_anti_spoof(uint16_t port, uint16_t vf, uint8_t on);
81 
98 int rte_pmd_ixgbe_set_vf_vlan_insert(uint16_t port, uint16_t vf,
99  uint16_t vlan_id);
100 
115 int rte_pmd_ixgbe_set_tx_loopback(uint16_t port, uint8_t on);
116 
131 int rte_pmd_ixgbe_set_all_queues_drop_en(uint16_t port, uint8_t on);
132 
150 int rte_pmd_ixgbe_set_vf_split_drop_en(uint16_t port, uint16_t vf, uint8_t on);
151 
169 int
170 rte_pmd_ixgbe_set_vf_vlan_stripq(uint16_t port, uint16_t vf, uint8_t on);
171 
188 int rte_pmd_ixgbe_macsec_enable(uint16_t port, uint8_t en, uint8_t rp);
189 
200 int rte_pmd_ixgbe_macsec_disable(uint16_t port);
201 
214 int rte_pmd_ixgbe_macsec_config_txsc(uint16_t port, uint8_t *mac);
215 
230 int rte_pmd_ixgbe_macsec_config_rxsc(uint16_t port, uint8_t *mac, uint16_t pi);
231 
251 int rte_pmd_ixgbe_macsec_select_txsa(uint16_t port, uint8_t idx, uint8_t an,
252  uint32_t pn, uint8_t *key);
253 
273 int rte_pmd_ixgbe_macsec_select_rxsa(uint16_t port, uint8_t idx, uint8_t an,
274  uint32_t pn, uint8_t *key);
275 
298 int
299 rte_pmd_ixgbe_set_vf_rxmode(uint16_t port, uint16_t vf, uint16_t rx_mask,
300  uint8_t on);
301 
318 int
319 rte_pmd_ixgbe_set_vf_rx(uint16_t port, uint16_t vf, uint8_t on);
320 
337 int
338 rte_pmd_ixgbe_set_vf_tx(uint16_t port, uint16_t vf, uint8_t on);
339 
359 int
360 rte_pmd_ixgbe_set_vf_vlan_filter(uint16_t port, uint16_t vlan,
361  uint64_t vf_mask, uint8_t vlan_on);
362 
380 int rte_pmd_ixgbe_set_vf_rate_limit(uint16_t port, uint16_t vf,
381  uint16_t tx_rate, uint64_t q_msk);
382 
403  uint8_t tc_num,
404  uint8_t *bw_weight);
405 
406 
418 int rte_pmd_ixgbe_bypass_init(uint16_t port);
419 
435 int rte_pmd_ixgbe_bypass_state_show(uint16_t port, uint32_t *state);
436 
452 int rte_pmd_ixgbe_bypass_state_set(uint16_t port, uint32_t *new_state);
453 
477  uint32_t event,
478  uint32_t *state);
479 
503  uint32_t event,
504  uint32_t state);
505 
526 int rte_pmd_ixgbe_bypass_wd_timeout_store(uint16_t port, uint32_t timeout);
527 
540 int rte_pmd_ixgbe_bypass_ver_show(uint16_t port, uint32_t *ver);
541 
562 int rte_pmd_ixgbe_bypass_wd_timeout_show(uint16_t port, uint32_t *wd_timeout);
563 
574 int rte_pmd_ixgbe_bypass_wd_reset(uint16_t port);
575 
587 int __rte_experimental
588 rte_pmd_ixgbe_mdio_lock(uint16_t port);
589 
600 int __rte_experimental
602 
621 int __rte_experimental
622 rte_pmd_ixgbe_mdio_unlocked_read(uint16_t port, uint32_t reg_addr,
623  uint32_t dev_type, uint16_t *phy_data);
624 
644 int __rte_experimental
645 rte_pmd_ixgbe_mdio_unlocked_write(uint16_t port, uint32_t reg_addr,
646  uint32_t dev_type, uint16_t phy_data);
647 
656 };
657 
662  uint16_t vfid;
663  uint16_t msg_type;
664  uint16_t retval;
665  void *msg;
666 };
667 enum {
668  RTE_PMD_IXGBE_BYPASS_MODE_NONE,
669  RTE_PMD_IXGBE_BYPASS_MODE_NORMAL,
670  RTE_PMD_IXGBE_BYPASS_MODE_BYPASS,
671  RTE_PMD_IXGBE_BYPASS_MODE_ISOLATE,
672  RTE_PMD_IXGBE_BYPASS_MODE_NUM,
673 };
674 
675 #define RTE_PMD_IXGBE_BYPASS_MODE_VALID(x) \
676  ((x) > RTE_PMD_IXGBE_BYPASS_MODE_NONE && \
677  (x) < RTE_PMD_IXGBE_BYPASS_MODE_NUM)
678 
679 enum {
680  RTE_PMD_IXGBE_BYPASS_EVENT_NONE,
681  RTE_PMD_IXGBE_BYPASS_EVENT_START,
682  RTE_PMD_IXGBE_BYPASS_EVENT_OS_ON = RTE_PMD_IXGBE_BYPASS_EVENT_START,
683  RTE_PMD_IXGBE_BYPASS_EVENT_POWER_ON,
684  RTE_PMD_IXGBE_BYPASS_EVENT_OS_OFF,
685  RTE_PMD_IXGBE_BYPASS_EVENT_POWER_OFF,
686  RTE_PMD_IXGBE_BYPASS_EVENT_TIMEOUT,
687  RTE_PMD_IXGBE_BYPASS_EVENT_NUM
688 };
689 
690 #define RTE_PMD_IXGBE_BYPASS_EVENT_VALID(x) \
691  ((x) > RTE_PMD_IXGBE_BYPASS_EVENT_NONE && \
692  (x) < RTE_PMD_IXGBE_BYPASS_MODE_NUM)
693 
694 enum {
695  RTE_PMD_IXGBE_BYPASS_TMT_OFF, /* timeout disabled. */
696  RTE_PMD_IXGBE_BYPASS_TMT_1_5_SEC, /* timeout for 1.5 seconds */
697  RTE_PMD_IXGBE_BYPASS_TMT_2_SEC, /* timeout for 2 seconds */
698  RTE_PMD_IXGBE_BYPASS_TMT_3_SEC, /* timeout for 3 seconds */
699  RTE_PMD_IXGBE_BYPASS_TMT_4_SEC, /* timeout for 4 seconds */
700  RTE_PMD_IXGBE_BYPASS_TMT_8_SEC, /* timeout for 8 seconds */
701  RTE_PMD_IXGBE_BYPASS_TMT_16_SEC, /* timeout for 16 seconds */
702  RTE_PMD_IXGBE_BYPASS_TMT_32_SEC, /* timeout for 32 seconds */
703  RTE_PMD_IXGBE_BYPASS_TMT_NUM
704 };
705 
706 #define RTE_PMD_IXGBE_BYPASS_TMT_VALID(x) \
707  ((x) == RTE_PMD_IXGBE_BYPASS_TMT_OFF || \
708  ((x) > RTE_PMD_IXGBE_BYPASS_TMT_OFF && \
709  (x) < RTE_PMD_IXGBE_BYPASS_TMT_NUM))
710 
722 int __rte_experimental
723 rte_pmd_ixgbe_upd_fctrl_sbp(uint16_t port, int enable);
724 #endif /* _PMD_IXGBE_H_ */