DPDK  18.05.1
rte_eth_ctrl.h
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1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2015 Intel Corporation
3  */
4 
5 #ifndef _RTE_ETH_CTRL_H_
6 #define _RTE_ETH_CTRL_H_
7 
8 #include <stdint.h>
9 #include <rte_common.h>
10 #include "rte_ether.h"
11 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
24 /*
25  * A packet can be identified by hardware as different flow types. Different
26  * NIC hardwares may support different flow types.
27  * Basically, the NIC hardware identifies the flow type as deep protocol as
28  * possible, and exclusively. For example, if a packet is identified as
29  * 'RTE_ETH_FLOW_NONFRAG_IPV4_TCP', it will not be any of other flow types,
30  * though it is an actual IPV4 packet.
31  * Note that the flow types are used to define RSS offload types in
32  * rte_ethdev.h.
33  */
34 #define RTE_ETH_FLOW_UNKNOWN 0
35 #define RTE_ETH_FLOW_RAW 1
36 #define RTE_ETH_FLOW_IPV4 2
37 #define RTE_ETH_FLOW_FRAG_IPV4 3
38 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4
39 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5
40 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6
41 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7
42 #define RTE_ETH_FLOW_IPV6 8
43 #define RTE_ETH_FLOW_FRAG_IPV6 9
44 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10
45 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11
46 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12
47 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13
48 #define RTE_ETH_FLOW_L2_PAYLOAD 14
49 #define RTE_ETH_FLOW_IPV6_EX 15
50 #define RTE_ETH_FLOW_IPV6_TCP_EX 16
51 #define RTE_ETH_FLOW_IPV6_UDP_EX 17
52 #define RTE_ETH_FLOW_PORT 18
53 
54 #define RTE_ETH_FLOW_VXLAN 19
55 #define RTE_ETH_FLOW_GENEVE 20
56 #define RTE_ETH_FLOW_NVGRE 21
57 #define RTE_ETH_FLOW_VXLAN_GPE 22
58 #define RTE_ETH_FLOW_MAX 23
59 
63 enum rte_filter_type {
64  RTE_ETH_FILTER_NONE = 0,
65  RTE_ETH_FILTER_MACVLAN,
66  RTE_ETH_FILTER_ETHERTYPE,
67  RTE_ETH_FILTER_FLEXIBLE,
68  RTE_ETH_FILTER_SYN,
69  RTE_ETH_FILTER_NTUPLE,
70  RTE_ETH_FILTER_TUNNEL,
71  RTE_ETH_FILTER_FDIR,
72  RTE_ETH_FILTER_HASH,
73  RTE_ETH_FILTER_L2_TUNNEL,
74  RTE_ETH_FILTER_GENERIC,
75  RTE_ETH_FILTER_MAX
76 };
77 
81 enum rte_filter_op {
83  RTE_ETH_FILTER_NOP = 0,
84  RTE_ETH_FILTER_ADD,
85  RTE_ETH_FILTER_UPDATE,
86  RTE_ETH_FILTER_DELETE,
87  RTE_ETH_FILTER_FLUSH,
88  RTE_ETH_FILTER_GET,
89  RTE_ETH_FILTER_SET,
90  RTE_ETH_FILTER_INFO,
91  RTE_ETH_FILTER_STATS,
92  RTE_ETH_FILTER_OP_MAX
93 };
94 
98 enum rte_mac_filter_type {
99  RTE_MAC_PERFECT_MATCH = 1,
100  RTE_MACVLAN_PERFECT_MATCH,
101  RTE_MAC_HASH_MATCH,
103  RTE_MACVLAN_HASH_MATCH,
104 };
105 
109 struct rte_eth_mac_filter {
110  uint8_t is_vf;
111  uint16_t dst_id;
112  enum rte_mac_filter_type filter_type;
113  struct ether_addr mac_addr;
114 };
115 
120 #define RTE_ETHTYPE_FLAGS_MAC 0x0001
121 #define RTE_ETHTYPE_FLAGS_DROP 0x0002
128 struct rte_eth_ethertype_filter {
129  struct ether_addr mac_addr;
130  uint16_t ether_type;
131  uint16_t flags;
132  uint16_t queue;
133 };
134 
135 #define RTE_FLEX_FILTER_MAXLEN 128
136 #define RTE_FLEX_FILTER_MASK_SIZE \
137  (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
138 
145 struct rte_eth_flex_filter {
146  uint16_t len;
147  uint8_t bytes[RTE_FLEX_FILTER_MAXLEN];
148  uint8_t mask[RTE_FLEX_FILTER_MASK_SIZE];
150  uint8_t priority;
151  uint16_t queue;
152 };
153 
159 struct rte_eth_syn_filter {
160  uint8_t hig_pri;
162  uint16_t queue;
163 };
164 
169 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
170 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
171 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
172 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
173 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
174 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
176 #define RTE_5TUPLE_FLAGS ( \
177  RTE_NTUPLE_FLAGS_DST_IP | \
178  RTE_NTUPLE_FLAGS_SRC_IP | \
179  RTE_NTUPLE_FLAGS_DST_PORT | \
180  RTE_NTUPLE_FLAGS_SRC_PORT | \
181  RTE_NTUPLE_FLAGS_PROTO)
182 
183 #define RTE_2TUPLE_FLAGS ( \
184  RTE_NTUPLE_FLAGS_DST_PORT | \
185  RTE_NTUPLE_FLAGS_PROTO)
186 
187 #define TCP_URG_FLAG 0x20
188 #define TCP_ACK_FLAG 0x10
189 #define TCP_PSH_FLAG 0x08
190 #define TCP_RST_FLAG 0x04
191 #define TCP_SYN_FLAG 0x02
192 #define TCP_FIN_FLAG 0x01
193 #define TCP_FLAG_ALL 0x3F
194 
200 struct rte_eth_ntuple_filter {
201  uint16_t flags;
202  uint32_t dst_ip;
203  uint32_t dst_ip_mask;
204  uint32_t src_ip;
205  uint32_t src_ip_mask;
206  uint16_t dst_port;
207  uint16_t dst_port_mask;
208  uint16_t src_port;
209  uint16_t src_port_mask;
210  uint8_t proto;
211  uint8_t proto_mask;
215  uint8_t tcp_flags;
216  uint16_t priority;
218  uint16_t queue;
219 };
220 
224 enum rte_eth_tunnel_type {
225  RTE_TUNNEL_TYPE_NONE = 0,
226  RTE_TUNNEL_TYPE_VXLAN,
227  RTE_TUNNEL_TYPE_GENEVE,
228  RTE_TUNNEL_TYPE_TEREDO,
229  RTE_TUNNEL_TYPE_NVGRE,
230  RTE_TUNNEL_TYPE_IP_IN_GRE,
231  RTE_L2_TUNNEL_TYPE_E_TAG,
232  RTE_TUNNEL_TYPE_MAX,
233 };
234 
238 #define ETH_TUNNEL_FILTER_OMAC 0x01
239 #define ETH_TUNNEL_FILTER_OIP 0x02
240 #define ETH_TUNNEL_FILTER_TENID 0x04
241 #define ETH_TUNNEL_FILTER_IMAC 0x08
242 #define ETH_TUNNEL_FILTER_IVLAN 0x10
243 #define ETH_TUNNEL_FILTER_IIP 0x20
245 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
246  ETH_TUNNEL_FILTER_IVLAN)
247 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
248  ETH_TUNNEL_FILTER_IVLAN | \
249  ETH_TUNNEL_FILTER_TENID)
250 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
251  ETH_TUNNEL_FILTER_TENID)
252 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
253  ETH_TUNNEL_FILTER_TENID | \
254  ETH_TUNNEL_FILTER_IMAC)
255 
259 enum rte_tunnel_iptype {
260  RTE_TUNNEL_IPTYPE_IPV4 = 0,
261  RTE_TUNNEL_IPTYPE_IPV6,
262 };
263 
267 struct rte_eth_tunnel_filter_conf {
268  struct ether_addr outer_mac;
269  struct ether_addr inner_mac;
270  uint16_t inner_vlan;
271  enum rte_tunnel_iptype ip_type;
275  union {
276  uint32_t ipv4_addr;
277  uint32_t ipv6_addr[4];
278  } ip_addr;
280  uint16_t filter_type;
281  enum rte_eth_tunnel_type tunnel_type;
282  uint32_t tenant_id;
283  uint16_t queue_id;
284 };
285 
289 enum rte_eth_global_cfg_type {
290  RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
291  RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
292  RTE_ETH_GLOBAL_CFG_TYPE_MAX,
293 };
294 
298 struct rte_eth_global_cfg {
299  enum rte_eth_global_cfg_type cfg_type;
300  union {
301  uint8_t gre_key_len;
302  uint64_t reserved;
303  } cfg;
304 };
305 
306 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
307 #define RTE_ETH_INSET_SIZE_MAX 128
312 enum rte_eth_input_set_field {
313  RTE_ETH_INPUT_SET_UNKNOWN = 0,
314 
315  /* L2 */
316  RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
317  RTE_ETH_INPUT_SET_L2_DST_MAC,
318  RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
319  RTE_ETH_INPUT_SET_L2_INNER_VLAN,
320  RTE_ETH_INPUT_SET_L2_ETHERTYPE,
321 
322  /* L3 */
323  RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
324  RTE_ETH_INPUT_SET_L3_DST_IP4,
325  RTE_ETH_INPUT_SET_L3_SRC_IP6,
326  RTE_ETH_INPUT_SET_L3_DST_IP6,
327  RTE_ETH_INPUT_SET_L3_IP4_TOS,
328  RTE_ETH_INPUT_SET_L3_IP4_PROTO,
329  RTE_ETH_INPUT_SET_L3_IP6_TC,
330  RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
331  RTE_ETH_INPUT_SET_L3_IP4_TTL,
332  RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
333 
334  /* L4 */
335  RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
336  RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
337  RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
338  RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
339  RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
340  RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
341  RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
342 
343  /* Tunnel */
344  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
345  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
346  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
347  RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
348  RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
349 
350  /* Flexible Payload */
351  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
352  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
353  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
354  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
355  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
356  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
357  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
358  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
359 
360  RTE_ETH_INPUT_SET_DEFAULT = 65533,
361  RTE_ETH_INPUT_SET_NONE = 65534,
362  RTE_ETH_INPUT_SET_MAX = 65535,
363 };
364 
368 enum rte_filter_input_set_op {
369  RTE_ETH_INPUT_SET_OP_UNKNOWN,
370  RTE_ETH_INPUT_SET_SELECT,
371  RTE_ETH_INPUT_SET_ADD,
372  RTE_ETH_INPUT_SET_OP_MAX
373 };
374 
375 
380 struct rte_eth_input_set_conf {
381  uint16_t flow_type;
382  uint16_t inset_size;
383  enum rte_eth_input_set_field field[RTE_ETH_INSET_SIZE_MAX];
384  enum rte_filter_input_set_op op;
385 };
386 
390 struct rte_eth_l2_flow {
391  uint16_t ether_type;
392 };
393 
397 struct rte_eth_ipv4_flow {
398  uint32_t src_ip;
399  uint32_t dst_ip;
400  uint8_t tos;
401  uint8_t ttl;
402  uint8_t proto;
403 };
404 
408 struct rte_eth_udpv4_flow {
409  struct rte_eth_ipv4_flow ip;
410  uint16_t src_port;
411  uint16_t dst_port;
412 };
413 
417 struct rte_eth_tcpv4_flow {
418  struct rte_eth_ipv4_flow ip;
419  uint16_t src_port;
420  uint16_t dst_port;
421 };
422 
426 struct rte_eth_sctpv4_flow {
427  struct rte_eth_ipv4_flow ip;
428  uint16_t src_port;
429  uint16_t dst_port;
430  uint32_t verify_tag;
431 };
432 
436 struct rte_eth_ipv6_flow {
437  uint32_t src_ip[4];
438  uint32_t dst_ip[4];
439  uint8_t tc;
440  uint8_t proto;
441  uint8_t hop_limits;
442 };
443 
447 struct rte_eth_udpv6_flow {
448  struct rte_eth_ipv6_flow ip;
449  uint16_t src_port;
450  uint16_t dst_port;
451 };
452 
456 struct rte_eth_tcpv6_flow {
457  struct rte_eth_ipv6_flow ip;
458  uint16_t src_port;
459  uint16_t dst_port;
460 };
461 
465 struct rte_eth_sctpv6_flow {
466  struct rte_eth_ipv6_flow ip;
467  uint16_t src_port;
468  uint16_t dst_port;
469  uint32_t verify_tag;
470 };
471 
475 struct rte_eth_mac_vlan_flow {
476  struct ether_addr mac_addr;
477 };
478 
482 enum rte_eth_fdir_tunnel_type {
483  RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
484  RTE_FDIR_TUNNEL_TYPE_NVGRE,
485  RTE_FDIR_TUNNEL_TYPE_VXLAN,
486 };
487 
492 struct rte_eth_tunnel_flow {
493  enum rte_eth_fdir_tunnel_type tunnel_type;
495  uint32_t tunnel_id;
496  struct ether_addr mac_addr;
497 };
498 
503 union rte_eth_fdir_flow {
504  struct rte_eth_l2_flow l2_flow;
505  struct rte_eth_udpv4_flow udp4_flow;
506  struct rte_eth_tcpv4_flow tcp4_flow;
507  struct rte_eth_sctpv4_flow sctp4_flow;
508  struct rte_eth_ipv4_flow ip4_flow;
509  struct rte_eth_udpv6_flow udp6_flow;
510  struct rte_eth_tcpv6_flow tcp6_flow;
511  struct rte_eth_sctpv6_flow sctp6_flow;
512  struct rte_eth_ipv6_flow ipv6_flow;
513  struct rte_eth_mac_vlan_flow mac_vlan_flow;
514  struct rte_eth_tunnel_flow tunnel_flow;
515 };
516 
520 struct rte_eth_fdir_flow_ext {
521  uint16_t vlan_tci;
522  uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
524  uint8_t is_vf;
525  uint16_t dst_id;
526 };
527 
531 struct rte_eth_fdir_input {
532  uint16_t flow_type;
533  union rte_eth_fdir_flow flow;
535  struct rte_eth_fdir_flow_ext flow_ext;
537 };
538 
542 enum rte_eth_fdir_behavior {
543  RTE_ETH_FDIR_ACCEPT = 0,
544  RTE_ETH_FDIR_REJECT,
545  RTE_ETH_FDIR_PASSTHRU,
546 };
547 
552 enum rte_eth_fdir_status {
553  RTE_ETH_FDIR_NO_REPORT_STATUS = 0,
554  RTE_ETH_FDIR_REPORT_ID,
555  RTE_ETH_FDIR_REPORT_ID_FLEX_4,
556  RTE_ETH_FDIR_REPORT_FLEX_8,
557 };
558 
562 struct rte_eth_fdir_action {
563  uint16_t rx_queue;
564  enum rte_eth_fdir_behavior behavior;
565  enum rte_eth_fdir_status report_status;
566  uint8_t flex_off;
570 };
571 
577 struct rte_eth_fdir_filter {
578  uint32_t soft_id;
580  struct rte_eth_fdir_input input;
581  struct rte_eth_fdir_action action;
582 };
583 
588 struct rte_eth_fdir_masks {
589  uint16_t vlan_tci_mask;
591  struct rte_eth_ipv4_flow ipv4_mask;
593  struct rte_eth_ipv6_flow ipv6_mask;
595  uint16_t src_port_mask;
597  uint16_t dst_port_mask;
600  uint8_t mac_addr_byte_mask;
602  uint32_t tunnel_id_mask;
603  uint8_t tunnel_type_mask;
605 };
606 
610 enum rte_eth_payload_type {
611  RTE_ETH_PAYLOAD_UNKNOWN = 0,
612  RTE_ETH_RAW_PAYLOAD,
613  RTE_ETH_L2_PAYLOAD,
614  RTE_ETH_L3_PAYLOAD,
615  RTE_ETH_L4_PAYLOAD,
616  RTE_ETH_PAYLOAD_MAX = 8,
617 };
618 
623 struct rte_eth_flex_payload_cfg {
624  enum rte_eth_payload_type type;
625  uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN];
630 };
631 
636 struct rte_eth_fdir_flex_mask {
637  uint16_t flow_type;
638  uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN];
640 };
641 
646 struct rte_eth_fdir_flex_conf {
647  uint16_t nb_payloads;
648  uint16_t nb_flexmasks;
649  struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
651  struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
653 };
654 
658 enum rte_fdir_mode {
659  RTE_FDIR_MODE_NONE = 0,
660  RTE_FDIR_MODE_SIGNATURE,
661  RTE_FDIR_MODE_PERFECT,
662  RTE_FDIR_MODE_PERFECT_MAC_VLAN,
663  RTE_FDIR_MODE_PERFECT_TUNNEL,
664 };
665 
666 #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
667 #define RTE_FLOW_MASK_ARRAY_SIZE \
668  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
669 
677 struct rte_eth_fdir_info {
678  enum rte_fdir_mode mode;
679  struct rte_eth_fdir_masks mask;
681  struct rte_eth_fdir_flex_conf flex_conf;
682  uint32_t guarant_spc;
683  uint32_t best_spc;
685  uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
686  uint32_t max_flexpayload;
689  uint32_t flex_payload_unit;
692  uint32_t max_flex_payload_segment_num;
696  uint16_t flex_payload_limit;
699  uint32_t flex_bitmask_unit;
701  uint32_t max_flex_bitmask_num;
702 };
703 
708 struct rte_eth_fdir_stats {
709  uint32_t collision;
710  uint32_t free;
711  uint32_t maxhash;
714  uint32_t maxlen;
715  uint64_t add;
716  uint64_t remove;
717  uint64_t f_add;
718  uint64_t f_remove;
719  uint32_t guarant_cnt;
720  uint32_t best_cnt;
721 };
722 
726 enum rte_eth_fdir_filter_info_type {
727  RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
729  RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT,
730  RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
731 };
732 
737 struct rte_eth_fdir_filter_info {
738  enum rte_eth_fdir_filter_info_type info_type;
740  union {
742  struct rte_eth_input_set_conf input_set_conf;
743  } info;
744 };
745 
756 enum rte_eth_hash_filter_info_type {
757  RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
759  RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT,
761  RTE_ETH_HASH_FILTER_GLOBAL_CONFIG,
763  RTE_ETH_HASH_FILTER_INPUT_SET_SELECT,
764  RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
765 };
766 
770 enum rte_eth_hash_function {
771  RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
772  RTE_ETH_HASH_FUNCTION_TOEPLITZ,
773  RTE_ETH_HASH_FUNCTION_SIMPLE_XOR,
774  RTE_ETH_HASH_FUNCTION_MAX,
775 };
776 
777 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \
778  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
779 
788 struct rte_eth_hash_global_conf {
789  enum rte_eth_hash_function hash_func;
791  uint64_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
793  uint64_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
794 };
795 
800 struct rte_eth_hash_filter_info {
801  enum rte_eth_hash_filter_info_type info_type;
803  union {
805  uint8_t enable;
807  struct rte_eth_hash_global_conf global_conf;
809  struct rte_eth_input_set_conf input_set_conf;
810  } info;
811 };
812 
816 struct rte_eth_l2_tunnel_conf {
817  enum rte_eth_tunnel_type l2_tunnel_type;
818  uint16_t ether_type; /* ether type in l2 header */
819  uint32_t tunnel_id; /* port tag id for e-tag */
820  uint16_t vf_id; /* VF id for tag insertion */
821  uint32_t pool; /* destination pool for tag based forwarding */
822 };
823 
824 #ifdef __cplusplus
825 }
826 #endif
827 
828 #endif /* _RTE_ETH_CTRL_H_ */
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