DPDK  18.02.2
rte_tm.h
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1 /*-
2  * BSD LICENSE
3  *
4  * Copyright(c) 2017 Intel Corporation.
5  * Copyright(c) 2017 Cavium.
6  * Copyright(c) 2017 NXP.
7  * All rights reserved.
8  *
9  * Redistribution and use in source and binary forms, with or without
10  * modification, are permitted provided that the following conditions
11  * are met:
12  *
13  * * Redistributions of source code must retain the above copyright
14  * notice, this list of conditions and the following disclaimer.
15  * * Redistributions in binary form must reproduce the above copyright
16  * notice, this list of conditions and the following disclaimer in
17  * the documentation and/or other materials provided with the
18  * distribution.
19  * * Neither the name of Intel Corporation nor the names of its
20  * contributors may be used to endorse or promote products derived
21  * from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
26  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
27  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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29  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
30  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
31  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
32  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #ifndef __INCLUDE_RTE_TM_H__
37 #define __INCLUDE_RTE_TM_H__
38 
51 #include <stdint.h>
52 
53 #include <rte_common.h>
54 
55 #ifdef __cplusplus
56 extern "C" {
57 #endif
58 
72 #define RTE_TM_ETH_FRAMING_OVERHEAD 20
73 
84 #define RTE_TM_ETH_FRAMING_OVERHEAD_FCS 24
85 
93 #define RTE_TM_WRED_PROFILE_ID_NONE UINT32_MAX
94 
102 #define RTE_TM_SHAPER_PROFILE_ID_NONE UINT32_MAX
103 
109 #define RTE_TM_NODE_ID_NULL UINT32_MAX
110 
116 #define RTE_TM_NODE_LEVEL_ID_ANY UINT32_MAX
117 
121 enum rte_tm_color {
122  RTE_TM_GREEN = 0,
123  RTE_TM_YELLOW,
124  RTE_TM_RED,
125  RTE_TM_COLORS
126 };
127 
131 enum rte_tm_stats_type {
133  RTE_TM_STATS_N_PKTS = 1 << 0,
134 
136  RTE_TM_STATS_N_BYTES = 1 << 1,
137 
139  RTE_TM_STATS_N_PKTS_GREEN_DROPPED = 1 << 2,
140 
142  RTE_TM_STATS_N_PKTS_YELLOW_DROPPED = 1 << 3,
143 
145  RTE_TM_STATS_N_PKTS_RED_DROPPED = 1 << 4,
146 
148  RTE_TM_STATS_N_BYTES_GREEN_DROPPED = 1 << 5,
149 
151  RTE_TM_STATS_N_BYTES_YELLOW_DROPPED = 1 << 6,
152 
154  RTE_TM_STATS_N_BYTES_RED_DROPPED = 1 << 7,
155 
159  RTE_TM_STATS_N_PKTS_QUEUED = 1 << 8,
160 
164  RTE_TM_STATS_N_BYTES_QUEUED = 1 << 9,
165 };
166 
170 struct rte_tm_node_stats {
172  uint64_t n_pkts;
173 
175  uint64_t n_bytes;
176 
178  struct {
182  uint64_t n_pkts_dropped[RTE_TM_COLORS];
183 
187  uint64_t n_bytes_dropped[RTE_TM_COLORS];
188 
192  uint64_t n_pkts_queued;
193 
197  uint64_t n_bytes_queued;
198  } leaf;
199 };
200 
204 enum rte_tm_dynamic_update_type {
209  RTE_TM_UPDATE_NODE_PARENT_KEEP_LEVEL = 1 << 0,
210 
215  RTE_TM_UPDATE_NODE_PARENT_CHANGE_LEVEL = 1 << 1,
216 
218  RTE_TM_UPDATE_NODE_ADD_DELETE = 1 << 2,
219 
221  RTE_TM_UPDATE_NODE_SUSPEND_RESUME = 1 << 3,
222 
224  RTE_TM_UPDATE_NODE_WFQ_WEIGHT_MODE = 1 << 4,
225 
227  RTE_TM_UPDATE_NODE_N_SP_PRIORITIES = 1 << 5,
228 
230  RTE_TM_UPDATE_NODE_CMAN = 1 << 6,
231 
233  RTE_TM_UPDATE_NODE_STATS = 1 << 7,
234 };
235 
239 struct rte_tm_capabilities {
241  uint32_t n_nodes_max;
242 
246  uint32_t n_levels_max;
247 
251  int non_leaf_nodes_identical;
252 
256  int leaf_nodes_identical;
257 
264  uint32_t shaper_n_max;
265 
270  uint32_t shaper_private_n_max;
271 
279  int shaper_private_dual_rate_n_max;
280 
284  uint64_t shaper_private_rate_min;
285 
289  uint64_t shaper_private_rate_max;
290 
294  uint32_t shaper_shared_n_max;
295 
299  uint32_t shaper_shared_n_nodes_per_shaper_max;
300 
307  uint32_t shaper_shared_n_shapers_per_node_max;
308 
313  uint32_t shaper_shared_dual_rate_n_max;
314 
318  uint64_t shaper_shared_rate_min;
319 
323  uint64_t shaper_shared_rate_max;
324 
328  int shaper_pkt_length_adjust_min;
329 
333  int shaper_pkt_length_adjust_max;
334 
340  uint32_t sched_n_children_max;
341 
350  uint32_t sched_sp_n_priorities_max;
351 
360  uint32_t sched_wfq_n_children_per_group_max;
361 
373  uint32_t sched_wfq_n_groups_max;
374 
378  uint32_t sched_wfq_weight_max;
379 
384  int cman_head_drop_supported;
385 
393  uint32_t cman_wred_context_n_max;
394 
400  uint32_t cman_wred_context_private_n_max;
401 
405  uint32_t cman_wred_context_shared_n_max;
406 
410  uint32_t cman_wred_context_shared_n_nodes_per_context_max;
411 
419  uint32_t cman_wred_context_shared_n_contexts_per_node_max;
420 
422  int mark_vlan_dei_supported[RTE_TM_COLORS];
423 
425  int mark_ip_ecn_tcp_supported[RTE_TM_COLORS];
426 
428  int mark_ip_ecn_sctp_supported[RTE_TM_COLORS];
429 
431  int mark_ip_dscp_supported[RTE_TM_COLORS];
432 
436  uint64_t dynamic_update_mask;
437 
441  uint64_t stats_mask;
442 };
443 
447 struct rte_tm_level_capabilities {
449  uint32_t n_nodes_max;
450 
455  uint32_t n_nodes_nonleaf_max;
456 
461  uint32_t n_nodes_leaf_max;
462 
467  int non_leaf_nodes_identical;
468 
473  int leaf_nodes_identical;
474 
475  RTE_STD_C11
476  union {
478  struct {
484  int shaper_private_supported;
485 
494  int shaper_private_dual_rate_supported;
495 
501  uint64_t shaper_private_rate_min;
502 
508  uint64_t shaper_private_rate_max;
509 
518  uint32_t shaper_shared_n_max;
519 
526  uint32_t sched_n_children_max;
527 
539  uint32_t sched_sp_n_priorities_max;
540 
551  uint32_t sched_wfq_n_children_per_group_max;
552 
570  uint32_t sched_wfq_n_groups_max;
571 
577  uint32_t sched_wfq_weight_max;
578 
586  uint64_t stats_mask;
587  } nonleaf;
588 
590  struct {
596  int shaper_private_supported;
597 
605  int shaper_private_dual_rate_supported;
606 
612  uint64_t shaper_private_rate_min;
613 
619  uint64_t shaper_private_rate_max;
620 
629  uint32_t shaper_shared_n_max;
630 
637  int cman_head_drop_supported;
638 
644  int cman_wred_context_private_supported;
645 
655  uint32_t cman_wred_context_shared_n_max;
656 
664  uint64_t stats_mask;
665  } leaf;
666  };
667 };
668 
672 struct rte_tm_node_capabilities {
674  int shaper_private_supported;
675 
679  int shaper_private_dual_rate_supported;
680 
685  uint64_t shaper_private_rate_min;
686 
691  uint64_t shaper_private_rate_max;
692 
697  uint32_t shaper_shared_n_max;
698 
699  RTE_STD_C11
700  union {
702  struct {
704  uint32_t sched_n_children_max;
705 
712  uint32_t sched_sp_n_priorities_max;
713 
721  uint32_t sched_wfq_n_children_per_group_max;
722 
735  uint32_t sched_wfq_n_groups_max;
736 
741  uint32_t sched_wfq_weight_max;
742  } nonleaf;
743 
745  struct {
747  int cman_head_drop_supported;
748 
750  int cman_wred_context_private_supported;
751 
757  uint32_t cman_wred_context_shared_n_max;
758  } leaf;
759  };
760 
764  uint64_t stats_mask;
765 };
766 
783 enum rte_tm_cman_mode {
784  RTE_TM_CMAN_TAIL_DROP = 0,
785  RTE_TM_CMAN_HEAD_DROP,
786  RTE_TM_CMAN_WRED,
787 };
788 
792 struct rte_tm_red_params {
794  uint16_t min_th;
795 
797  uint16_t max_th;
798 
802  uint16_t maxp_inv;
803 
805  uint16_t wq_log2;
806 };
807 
819 struct rte_tm_wred_params {
821  struct rte_tm_red_params red_params[RTE_TM_COLORS];
822 };
823 
827 struct rte_tm_token_bucket {
829  uint64_t rate;
830 
832  uint64_t size;
833 };
834 
853 struct rte_tm_shaper_params {
855  struct rte_tm_token_bucket committed;
856 
858  struct rte_tm_token_bucket peak;
859 
865  int32_t pkt_length_adjust;
866 };
867 
895 struct rte_tm_node_params {
900  uint32_t shaper_profile_id;
901 
903  uint32_t *shared_shaper_id;
904 
906  uint32_t n_shared_shapers;
907 
908  RTE_STD_C11
909  union {
911  struct {
918  int *wfq_weight_mode;
919 
921  uint32_t n_sp_priorities;
922  } nonleaf;
923 
925  struct {
927  enum rte_tm_cman_mode cman;
928 
932  struct {
938  uint32_t wred_profile_id;
939 
945  uint32_t *shared_wred_context_id;
946 
952  uint32_t n_shared_wred_contexts;
953  } wred;
954  } leaf;
955  };
956 
963  uint64_t stats_mask;
964 };
965 
972 enum rte_tm_error_type {
973  RTE_TM_ERROR_TYPE_NONE,
974  RTE_TM_ERROR_TYPE_UNSPECIFIED,
975  RTE_TM_ERROR_TYPE_CAPABILITIES,
976  RTE_TM_ERROR_TYPE_LEVEL_ID,
977  RTE_TM_ERROR_TYPE_WRED_PROFILE,
978  RTE_TM_ERROR_TYPE_WRED_PROFILE_GREEN,
979  RTE_TM_ERROR_TYPE_WRED_PROFILE_YELLOW,
980  RTE_TM_ERROR_TYPE_WRED_PROFILE_RED,
981  RTE_TM_ERROR_TYPE_WRED_PROFILE_ID,
982  RTE_TM_ERROR_TYPE_SHARED_WRED_CONTEXT_ID,
983  RTE_TM_ERROR_TYPE_SHAPER_PROFILE,
984  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_RATE,
985  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_COMMITTED_SIZE,
986  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_RATE,
987  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PEAK_SIZE,
988  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_PKT_ADJUST_LEN,
989  RTE_TM_ERROR_TYPE_SHAPER_PROFILE_ID,
990  RTE_TM_ERROR_TYPE_SHARED_SHAPER_ID,
991  RTE_TM_ERROR_TYPE_NODE_PARENT_NODE_ID,
992  RTE_TM_ERROR_TYPE_NODE_PRIORITY,
993  RTE_TM_ERROR_TYPE_NODE_WEIGHT,
994  RTE_TM_ERROR_TYPE_NODE_PARAMS,
995  RTE_TM_ERROR_TYPE_NODE_PARAMS_SHAPER_PROFILE_ID,
996  RTE_TM_ERROR_TYPE_NODE_PARAMS_SHARED_SHAPER_ID,
997  RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SHARED_SHAPERS,
998  RTE_TM_ERROR_TYPE_NODE_PARAMS_WFQ_WEIGHT_MODE,
999  RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SP_PRIORITIES,
1000  RTE_TM_ERROR_TYPE_NODE_PARAMS_CMAN,
1001  RTE_TM_ERROR_TYPE_NODE_PARAMS_WRED_PROFILE_ID,
1002  RTE_TM_ERROR_TYPE_NODE_PARAMS_SHARED_WRED_CONTEXT_ID,
1003  RTE_TM_ERROR_TYPE_NODE_PARAMS_N_SHARED_WRED_CONTEXTS,
1004  RTE_TM_ERROR_TYPE_NODE_PARAMS_STATS,
1005  RTE_TM_ERROR_TYPE_NODE_ID,
1006 };
1007 
1019 struct rte_tm_error {
1020  enum rte_tm_error_type type;
1021  const void *cause;
1022  const char *message;
1023 };
1024 
1042 int
1043 rte_tm_get_number_of_leaf_nodes(uint16_t port_id,
1044  uint32_t *n_leaf_nodes,
1045  struct rte_tm_error *error);
1046 
1066 int
1067 rte_tm_node_type_get(uint16_t port_id,
1068  uint32_t node_id,
1069  int *is_leaf,
1070  struct rte_tm_error *error);
1071 
1084 int
1085 rte_tm_capabilities_get(uint16_t port_id,
1086  struct rte_tm_capabilities *cap,
1087  struct rte_tm_error *error);
1088 
1104 int
1105 rte_tm_level_capabilities_get(uint16_t port_id,
1106  uint32_t level_id,
1107  struct rte_tm_level_capabilities *cap,
1108  struct rte_tm_error *error);
1109 
1124 int
1125 rte_tm_node_capabilities_get(uint16_t port_id,
1126  uint32_t node_id,
1127  struct rte_tm_node_capabilities *cap,
1128  struct rte_tm_error *error);
1129 
1149 int
1150 rte_tm_wred_profile_add(uint16_t port_id,
1151  uint32_t wred_profile_id,
1152  struct rte_tm_wred_params *profile,
1153  struct rte_tm_error *error);
1154 
1172 int
1173 rte_tm_wred_profile_delete(uint16_t port_id,
1174  uint32_t wred_profile_id,
1175  struct rte_tm_error *error);
1176 
1203 int
1204 rte_tm_shared_wred_context_add_update(uint16_t port_id,
1205  uint32_t shared_wred_context_id,
1206  uint32_t wred_profile_id,
1207  struct rte_tm_error *error);
1208 
1227 int
1228 rte_tm_shared_wred_context_delete(uint16_t port_id,
1229  uint32_t shared_wred_context_id,
1230  struct rte_tm_error *error);
1231 
1251 int
1252 rte_tm_shaper_profile_add(uint16_t port_id,
1253  uint32_t shaper_profile_id,
1254  struct rte_tm_shaper_params *profile,
1255  struct rte_tm_error *error);
1256 
1274 int
1275 rte_tm_shaper_profile_delete(uint16_t port_id,
1276  uint32_t shaper_profile_id,
1277  struct rte_tm_error *error);
1278 
1303 int
1304 rte_tm_shared_shaper_add_update(uint16_t port_id,
1305  uint32_t shared_shaper_id,
1306  uint32_t shaper_profile_id,
1307  struct rte_tm_error *error);
1308 
1326 int
1327 rte_tm_shared_shaper_delete(uint16_t port_id,
1328  uint32_t shared_shaper_id,
1329  struct rte_tm_error *error);
1330 
1394 int
1395 rte_tm_node_add(uint16_t port_id,
1396  uint32_t node_id,
1397  uint32_t parent_node_id,
1398  uint32_t priority,
1399  uint32_t weight,
1400  uint32_t level_id,
1401  struct rte_tm_node_params *params,
1402  struct rte_tm_error *error);
1403 
1427 int
1428 rte_tm_node_delete(uint16_t port_id,
1429  uint32_t node_id,
1430  struct rte_tm_error *error);
1431 
1451 int
1452 rte_tm_node_suspend(uint16_t port_id,
1453  uint32_t node_id,
1454  struct rte_tm_error *error);
1455 
1474 int
1475 rte_tm_node_resume(uint16_t port_id,
1476  uint32_t node_id,
1477  struct rte_tm_error *error);
1478 
1515 int
1516 rte_tm_hierarchy_commit(uint16_t port_id,
1517  int clear_on_fail,
1518  struct rte_tm_error *error);
1519 
1551 int
1552 rte_tm_node_parent_update(uint16_t port_id,
1553  uint32_t node_id,
1554  uint32_t parent_node_id,
1555  uint32_t priority,
1556  uint32_t weight,
1557  struct rte_tm_error *error);
1558 
1580 int
1581 rte_tm_node_shaper_update(uint16_t port_id,
1582  uint32_t node_id,
1583  uint32_t shaper_profile_id,
1584  struct rte_tm_error *error);
1585 
1607 int
1608 rte_tm_node_shared_shaper_update(uint16_t port_id,
1609  uint32_t node_id,
1610  uint32_t shared_shaper_id,
1611  int add,
1612  struct rte_tm_error *error);
1613 
1634 int
1635 rte_tm_node_stats_update(uint16_t port_id,
1636  uint32_t node_id,
1637  uint64_t stats_mask,
1638  struct rte_tm_error *error);
1639 
1662 int
1663 rte_tm_node_wfq_weight_mode_update(uint16_t port_id,
1664  uint32_t node_id,
1665  int *wfq_weight_mode,
1666  uint32_t n_sp_priorities,
1667  struct rte_tm_error *error);
1668 
1685 int
1686 rte_tm_node_cman_update(uint16_t port_id,
1687  uint32_t node_id,
1688  enum rte_tm_cman_mode cman,
1689  struct rte_tm_error *error);
1690 
1709 int
1710 rte_tm_node_wred_context_update(uint16_t port_id,
1711  uint32_t node_id,
1712  uint32_t wred_profile_id,
1713  struct rte_tm_error *error);
1714 
1734 int
1735 rte_tm_node_shared_wred_context_update(uint16_t port_id,
1736  uint32_t node_id,
1737  uint32_t shared_wred_context_id,
1738  int add,
1739  struct rte_tm_error *error);
1740 
1766 int
1767 rte_tm_node_stats_read(uint16_t port_id,
1768  uint32_t node_id,
1769  struct rte_tm_node_stats *stats,
1770  uint64_t *stats_mask,
1771  int clear,
1772  struct rte_tm_error *error);
1773 
1803 int
1804 rte_tm_mark_vlan_dei(uint16_t port_id,
1805  int mark_green,
1806  int mark_yellow,
1807  int mark_red,
1808  struct rte_tm_error *error);
1809 
1853 int
1854 rte_tm_mark_ip_ecn(uint16_t port_id,
1855  int mark_green,
1856  int mark_yellow,
1857  int mark_red,
1858  struct rte_tm_error *error);
1859 
1901 int
1902 rte_tm_mark_ip_dscp(uint16_t port_id,
1903  int mark_green,
1904  int mark_yellow,
1905  int mark_red,
1906  struct rte_tm_error *error);
1907 
1908 #ifdef __cplusplus
1909 }
1910 #endif
1911 
1912 #endif /* __INCLUDE_RTE_TM_H__ */
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