DPDK  18.02.2
rte_pmd_i40e.h
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1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2017 Intel Corporation
3  */
4 
5 #ifndef _PMD_I40E_H_
6 #define _PMD_I40E_H_
7 
17 #include <rte_ethdev_driver.h>
18 
22 enum rte_pmd_i40e_mb_event_rsp {
23  RTE_PMD_I40E_MB_EVENT_NOOP_ACK,
24  RTE_PMD_I40E_MB_EVENT_NOOP_NACK,
25  RTE_PMD_I40E_MB_EVENT_PROCEED,
26  RTE_PMD_I40E_MB_EVENT_MAX
27 };
28 
32 struct rte_pmd_i40e_mb_event_param {
33  uint16_t vfid;
34  uint16_t msg_type;
35  uint16_t retval;
36  void *msg;
37  uint16_t msglen;
38 };
39 
43 enum rte_pmd_i40e_package_op {
44  RTE_PMD_I40E_PKG_OP_UNDEFINED = 0,
45  RTE_PMD_I40E_PKG_OP_WR_ADD,
46  RTE_PMD_I40E_PKG_OP_WR_DEL,
47  RTE_PMD_I40E_PKG_OP_WR_ONLY,
48  RTE_PMD_I40E_PKG_OP_MAX = 32
49 };
50 
54 enum rte_pmd_i40e_package_info {
55  RTE_PMD_I40E_PKG_INFO_UNDEFINED = 0,
56  RTE_PMD_I40E_PKG_INFO_GLOBAL_HEADER,
57  RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES_SIZE,
58  RTE_PMD_I40E_PKG_INFO_GLOBAL_NOTES,
59  RTE_PMD_I40E_PKG_INFO_GLOBAL_MAX = 1024,
60  RTE_PMD_I40E_PKG_INFO_HEADER,
61  RTE_PMD_I40E_PKG_INFO_DEVID_NUM,
62  RTE_PMD_I40E_PKG_INFO_DEVID_LIST,
63  RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM,
64  RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST,
65  RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM,
66  RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST,
67  RTE_PMD_I40E_PKG_INFO_PTYPE_NUM,
68  RTE_PMD_I40E_PKG_INFO_PTYPE_LIST,
69  RTE_PMD_I40E_PKG_INFO_MAX = (int)0xFFFFFFFF
70 };
71 
75 enum rte_pmd_i40e_queue_region_op {
76  RTE_PMD_I40E_RSS_QUEUE_REGION_UNDEFINED,
78  RTE_PMD_I40E_RSS_QUEUE_REGION_SET,
80  RTE_PMD_I40E_RSS_QUEUE_REGION_FLOWTYPE_SET,
82  RTE_PMD_I40E_RSS_QUEUE_REGION_USER_PRIORITY_SET,
90  RTE_PMD_I40E_RSS_QUEUE_REGION_ALL_FLUSH_ON,
96  RTE_PMD_I40E_RSS_QUEUE_REGION_ALL_FLUSH_OFF,
97  RTE_PMD_I40E_RSS_QUEUE_REGION_INFO_GET,
98  RTE_PMD_I40E_RSS_QUEUE_REGION_OP_MAX
99 };
100 
101 #define RTE_PMD_I40E_DDP_NAME_SIZE 32
102 #define RTE_PMD_I40E_PCTYPE_MAX 64
103 #define RTE_PMD_I40E_REGION_MAX_NUM 8
104 #define RTE_PMD_I40E_MAX_USER_PRIORITY 8
105 
110 struct rte_pmd_i40e_ddp_version {
111  uint8_t major;
112  uint8_t minor;
113  uint8_t update;
114  uint8_t draft;
115 };
116 
120 struct rte_pmd_i40e_ddp_device_id {
121  uint32_t vendor_dev_id;
122  uint32_t sub_vendor_dev_id;
123 };
124 
128 struct rte_pmd_i40e_profile_info {
129  uint32_t track_id;
130  struct rte_pmd_i40e_ddp_version version;
131  uint8_t owner;
132  uint8_t reserved[7];
133  uint8_t name[RTE_PMD_I40E_DDP_NAME_SIZE];
134 };
135 
136 #define RTE_PMD_I40E_DDP_OWNER_UNKNOWN 0xFF
137 
141 struct rte_pmd_i40e_profile_list {
142  uint32_t p_count;
143  struct rte_pmd_i40e_profile_info p_info[1];
144 };
145 
146 #define RTE_PMD_I40E_PROTO_NUM 6
147 #define RTE_PMD_I40E_PROTO_UNUSED 0xFF
148 
152 struct rte_pmd_i40e_proto_info {
153  uint8_t proto_id;
154  char name[RTE_PMD_I40E_DDP_NAME_SIZE];
155 };
156 
160 struct rte_pmd_i40e_ptype_info {
161  uint8_t ptype_id;
162  uint8_t protocols[RTE_PMD_I40E_PROTO_NUM];
163 };
164 
170 #define RTE_PMD_I40E_PTYPE_USER_DEFINE_MASK 0x80000000
171 
172 struct rte_pmd_i40e_ptype_mapping {
173  uint16_t hw_ptype;
174  uint32_t sw_ptype;
175 };
176 
180 struct rte_pmd_i40e_queue_region_conf {
182  uint8_t region_id;
187  uint8_t hw_flowtype;
189  uint8_t queue_start_index;
191  uint8_t queue_num;
193  uint8_t user_priority;
194 };
195 
196 /* queue region info */
197 struct rte_pmd_i40e_queue_region_info {
199  uint8_t region_id;
201  uint8_t queue_start_index;
203  uint8_t queue_num;
205  uint8_t user_priority_num;
207  uint8_t user_priority[RTE_PMD_I40E_MAX_USER_PRIORITY];
209  uint8_t flowtype_num;
215  uint8_t hw_flowtype[RTE_PMD_I40E_PCTYPE_MAX];
216 };
217 
218 struct rte_pmd_i40e_queue_regions {
220  uint16_t queue_region_number;
221  struct rte_pmd_i40e_queue_region_info
222  region[RTE_PMD_I40E_REGION_MAX_NUM];
223 };
224 
228 enum rte_pmd_i40e_pkt_template_behavior {
229  RTE_PMD_I40E_PKT_TEMPLATE_ACCEPT,
230  RTE_PMD_I40E_PKT_TEMPLATE_REJECT,
231  RTE_PMD_I40E_PKT_TEMPLATE_PASSTHRU,
232 };
233 
238 enum rte_pmd_i40e_pkt_template_status {
240  RTE_PMD_I40E_PKT_TEMPLATE_NO_REPORT_STATUS,
242  RTE_PMD_I40E_PKT_TEMPLATE_REPORT_ID,
244  RTE_PMD_I40E_PKT_TEMPLATE_REPORT_ID_FLEX_4,
246  RTE_PMD_I40E_PKT_TEMPLATE_REPORT_FLEX_8,
247 };
248 
252 struct rte_pmd_i40e_pkt_template_action {
254  uint16_t rx_queue;
256  enum rte_pmd_i40e_pkt_template_behavior behavior;
258  enum rte_pmd_i40e_pkt_template_status report_status;
264  uint8_t flex_off;
265 };
266 
270 struct rte_pmd_i40e_pkt_template_input {
272  uint16_t pctype;
274  void *packet;
276  uint32_t length;
277 };
278 
283 struct rte_pmd_i40e_pkt_template_conf {
285  struct rte_pmd_i40e_pkt_template_input input;
287  struct rte_pmd_i40e_pkt_template_action action;
289  uint32_t soft_id;
290 };
291 
292 enum rte_pmd_i40e_inset_type {
293  INSET_NONE = 0,
294  INSET_HASH,
295  INSET_FDIR,
296  INSET_FDIR_FLX,
297 };
298 
299 struct rte_pmd_i40e_inset_mask {
300  uint8_t field_idx;
301  uint16_t mask;
302 };
303 
304 struct rte_pmd_i40e_inset {
305  uint64_t inset;
306  struct rte_pmd_i40e_inset_mask mask[2];
307 };
308 
324 int rte_pmd_i40e_flow_add_del_packet_template(
325  uint16_t port,
326  const struct rte_pmd_i40e_pkt_template_conf *conf,
327  uint8_t add);
328 
341 int rte_pmd_i40e_ping_vfs(uint16_t port, uint16_t vf);
342 
358 int rte_pmd_i40e_set_vf_mac_anti_spoof(uint16_t port,
359  uint16_t vf_id,
360  uint8_t on);
361 
377 int rte_pmd_i40e_set_vf_vlan_anti_spoof(uint16_t port,
378  uint16_t vf_id,
379  uint8_t on);
380 
394 int rte_pmd_i40e_set_tx_loopback(uint16_t port,
395  uint8_t on);
396 
412 int rte_pmd_i40e_set_vf_unicast_promisc(uint16_t port,
413  uint16_t vf_id,
414  uint8_t on);
415 
431 int rte_pmd_i40e_set_vf_multicast_promisc(uint16_t port,
432  uint16_t vf_id,
433  uint8_t on);
434 
455 int rte_pmd_i40e_set_vf_mac_addr(uint16_t port, uint16_t vf_id,
456  struct ether_addr *mac_addr);
457 
474 int
475 rte_pmd_i40e_set_vf_vlan_stripq(uint16_t port, uint16_t vf, uint8_t on);
476 
493 int rte_pmd_i40e_set_vf_vlan_insert(uint16_t port, uint16_t vf_id,
494  uint16_t vlan_id);
495 
512 int rte_pmd_i40e_set_vf_broadcast(uint16_t port, uint16_t vf_id,
513  uint8_t on);
514 
531 int rte_pmd_i40e_set_vf_vlan_tag(uint16_t port, uint16_t vf_id, uint8_t on);
532 
552 int rte_pmd_i40e_set_vf_vlan_filter(uint16_t port, uint16_t vlan_id,
553  uint64_t vf_mask, uint8_t on);
554 
577 int rte_pmd_i40e_get_vf_stats(uint16_t port,
578  uint16_t vf_id,
579  struct rte_eth_stats *stats);
580 
593 int rte_pmd_i40e_reset_vf_stats(uint16_t port,
594  uint16_t vf_id);
595 
618 int rte_pmd_i40e_set_vf_max_bw(uint16_t port,
619  uint16_t vf_id,
620  uint32_t bw);
621 
643 int rte_pmd_i40e_set_vf_tc_bw_alloc(uint16_t port,
644  uint16_t vf_id,
645  uint8_t tc_num,
646  uint8_t *bw_weight);
647 
668 int rte_pmd_i40e_set_vf_tc_max_bw(uint16_t port,
669  uint16_t vf_id,
670  uint8_t tc_no,
671  uint32_t bw);
672 
686 int rte_pmd_i40e_set_tc_strict_prio(uint16_t port, uint8_t tc_map);
687 
707 int rte_pmd_i40e_process_ddp_package(uint16_t port, uint8_t *buff,
708  uint32_t size,
709  enum rte_pmd_i40e_package_op op);
710 
728 int rte_pmd_i40e_get_ddp_info(uint8_t *pkg, uint32_t pkg_size,
729  uint8_t *info, uint32_t size,
730  enum rte_pmd_i40e_package_info type);
731 
745 int rte_pmd_i40e_get_ddp_list(uint16_t port, uint8_t *buff, uint32_t size);
746 
764 int rte_pmd_i40e_ptype_mapping_update(
765  uint16_t port,
766  struct rte_pmd_i40e_ptype_mapping *mapping_items,
767  uint16_t count,
768  uint8_t exclusive);
769 
777 int rte_pmd_i40e_ptype_mapping_reset(uint16_t port);
778 
795 int rte_pmd_i40e_ptype_mapping_get(
796  uint16_t port,
797  struct rte_pmd_i40e_ptype_mapping *mapping_items,
798  uint16_t size,
799  uint16_t *count,
800  uint8_t valid_only);
801 
816 int rte_pmd_i40e_ptype_mapping_replace(uint16_t port,
817  uint32_t target,
818  uint8_t mask,
819  uint32_t pkt_type);
820 
838 int rte_pmd_i40e_add_vf_mac_addr(uint16_t port, uint16_t vf_id,
839  struct ether_addr *mac_addr);
840 
841 #define RTE_PMD_I40E_PCTYPE_MAX 64
842 #define RTE_PMD_I40E_FLOW_TYPE_MAX 64
843 
844 struct rte_pmd_i40e_flow_type_mapping {
845  uint16_t flow_type;
846  uint64_t pctype;
847 };
848 
866 int rte_pmd_i40e_flow_type_mapping_update(
867  uint16_t port,
868  struct rte_pmd_i40e_flow_type_mapping *mapping_items,
869  uint16_t count,
870  uint8_t exclusive);
871 
883 int rte_pmd_i40e_flow_type_mapping_get(
884  uint16_t port,
885  struct rte_pmd_i40e_flow_type_mapping *mapping_items);
886 
894 int rte_pmd_i40e_flow_type_mapping_reset(uint16_t port);
895 
908 int rte_pmd_i40e_query_vfid_by_mac(uint16_t port,
909  const struct ether_addr *vf_mac);
910 
922 int rte_pmd_i40e_rss_queue_region_conf(uint16_t port_id,
923  enum rte_pmd_i40e_queue_region_op op_type, void *arg);
924 
925 int rte_pmd_i40e_cfg_hash_inset(uint16_t port,
926  uint64_t pctype, uint64_t inset);
927 
945 int rte_pmd_i40e_inset_get(uint16_t port, uint8_t pctype,
946  struct rte_pmd_i40e_inset *inset,
947  enum rte_pmd_i40e_inset_type inset_type);
948 
966 int rte_pmd_i40e_inset_set(uint16_t port, uint8_t pctype,
967  struct rte_pmd_i40e_inset *inset,
968  enum rte_pmd_i40e_inset_type inset_type);
969 
981 static inline int
982 rte_pmd_i40e_inset_field_get(uint64_t inset, uint8_t field_idx)
983 {
984  uint8_t bit_idx;
985 
986  if (field_idx > 63)
987  return 0;
988 
989  bit_idx = 63 - field_idx;
990  if (inset & (1ULL << bit_idx))
991  return 1;
992 
993  return 0;
994 }
995 
1007 static inline int
1008 rte_pmd_i40e_inset_field_set(uint64_t *inset, uint8_t field_idx)
1009 {
1010  uint8_t bit_idx;
1011 
1012  if (field_idx > 63)
1013  return -1;
1014 
1015  bit_idx = 63 - field_idx;
1016  *inset = *inset | (1ULL << bit_idx);
1017 
1018  return 0;
1019 }
1020 
1032 static inline int
1033 rte_pmd_i40e_inset_field_clear(uint64_t *inset, uint8_t field_idx)
1034 {
1035  uint8_t bit_idx;
1036 
1037  if (field_idx > 63)
1038  return -1;
1039 
1040  bit_idx = 63 - field_idx;
1041  *inset = *inset & ~(1ULL << bit_idx);
1042 
1043  return 0;
1044 }
1045 
1046 #endif /* _PMD_I40E_H_ */
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