DPDK  18.02.2
rte_eth_ctrl.h
Go to the documentation of this file.
1 /* SPDX-License-Identifier: BSD-3-Clause
2  * Copyright(c) 2010-2015 Intel Corporation
3  */
4 
5 #ifndef _RTE_ETH_CTRL_H_
6 #define _RTE_ETH_CTRL_H_
7 
8 #include <stdint.h>
9 #include <rte_common.h>
10 #include "rte_ether.h"
11 
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23 
24 /*
25  * A packet can be identified by hardware as different flow types. Different
26  * NIC hardwares may support different flow types.
27  * Basically, the NIC hardware identifies the flow type as deep protocol as
28  * possible, and exclusively. For example, if a packet is identified as
29  * 'RTE_ETH_FLOW_NONFRAG_IPV4_TCP', it will not be any of other flow types,
30  * though it is an actual IPV4 packet.
31  * Note that the flow types are used to define RSS offload types in
32  * rte_ethdev.h.
33  */
34 #define RTE_ETH_FLOW_UNKNOWN 0
35 #define RTE_ETH_FLOW_RAW 1
36 #define RTE_ETH_FLOW_IPV4 2
37 #define RTE_ETH_FLOW_FRAG_IPV4 3
38 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4
39 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5
40 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6
41 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7
42 #define RTE_ETH_FLOW_IPV6 8
43 #define RTE_ETH_FLOW_FRAG_IPV6 9
44 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10
45 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11
46 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12
47 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13
48 #define RTE_ETH_FLOW_L2_PAYLOAD 14
49 #define RTE_ETH_FLOW_IPV6_EX 15
50 #define RTE_ETH_FLOW_IPV6_TCP_EX 16
51 #define RTE_ETH_FLOW_IPV6_UDP_EX 17
52 #define RTE_ETH_FLOW_PORT 18
53 
54 #define RTE_ETH_FLOW_VXLAN 19
55 #define RTE_ETH_FLOW_GENEVE 20
56 #define RTE_ETH_FLOW_NVGRE 21
57 #define RTE_ETH_FLOW_MAX 22
58 
62 enum rte_filter_type {
63  RTE_ETH_FILTER_NONE = 0,
64  RTE_ETH_FILTER_MACVLAN,
65  RTE_ETH_FILTER_ETHERTYPE,
66  RTE_ETH_FILTER_FLEXIBLE,
67  RTE_ETH_FILTER_SYN,
68  RTE_ETH_FILTER_NTUPLE,
69  RTE_ETH_FILTER_TUNNEL,
70  RTE_ETH_FILTER_FDIR,
71  RTE_ETH_FILTER_HASH,
72  RTE_ETH_FILTER_L2_TUNNEL,
73  RTE_ETH_FILTER_GENERIC,
74  RTE_ETH_FILTER_MAX
75 };
76 
80 enum rte_filter_op {
82  RTE_ETH_FILTER_NOP = 0,
83  RTE_ETH_FILTER_ADD,
84  RTE_ETH_FILTER_UPDATE,
85  RTE_ETH_FILTER_DELETE,
86  RTE_ETH_FILTER_FLUSH,
87  RTE_ETH_FILTER_GET,
88  RTE_ETH_FILTER_SET,
89  RTE_ETH_FILTER_INFO,
90  RTE_ETH_FILTER_STATS,
91  RTE_ETH_FILTER_OP_MAX
92 };
93 
97 enum rte_mac_filter_type {
98  RTE_MAC_PERFECT_MATCH = 1,
99  RTE_MACVLAN_PERFECT_MATCH,
100  RTE_MAC_HASH_MATCH,
102  RTE_MACVLAN_HASH_MATCH,
103 };
104 
108 struct rte_eth_mac_filter {
109  uint8_t is_vf;
110  uint16_t dst_id;
111  enum rte_mac_filter_type filter_type;
112  struct ether_addr mac_addr;
113 };
114 
119 #define RTE_ETHTYPE_FLAGS_MAC 0x0001
120 #define RTE_ETHTYPE_FLAGS_DROP 0x0002
127 struct rte_eth_ethertype_filter {
128  struct ether_addr mac_addr;
129  uint16_t ether_type;
130  uint16_t flags;
131  uint16_t queue;
132 };
133 
134 #define RTE_FLEX_FILTER_MAXLEN 128
135 #define RTE_FLEX_FILTER_MASK_SIZE \
136  (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
137 
144 struct rte_eth_flex_filter {
145  uint16_t len;
146  uint8_t bytes[RTE_FLEX_FILTER_MAXLEN];
147  uint8_t mask[RTE_FLEX_FILTER_MASK_SIZE];
149  uint8_t priority;
150  uint16_t queue;
151 };
152 
158 struct rte_eth_syn_filter {
159  uint8_t hig_pri;
161  uint16_t queue;
162 };
163 
168 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
169 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
170 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
171 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
172 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
173 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
175 #define RTE_5TUPLE_FLAGS ( \
176  RTE_NTUPLE_FLAGS_DST_IP | \
177  RTE_NTUPLE_FLAGS_SRC_IP | \
178  RTE_NTUPLE_FLAGS_DST_PORT | \
179  RTE_NTUPLE_FLAGS_SRC_PORT | \
180  RTE_NTUPLE_FLAGS_PROTO)
181 
182 #define RTE_2TUPLE_FLAGS ( \
183  RTE_NTUPLE_FLAGS_DST_PORT | \
184  RTE_NTUPLE_FLAGS_PROTO)
185 
186 #define TCP_URG_FLAG 0x20
187 #define TCP_ACK_FLAG 0x10
188 #define TCP_PSH_FLAG 0x08
189 #define TCP_RST_FLAG 0x04
190 #define TCP_SYN_FLAG 0x02
191 #define TCP_FIN_FLAG 0x01
192 #define TCP_FLAG_ALL 0x3F
193 
199 struct rte_eth_ntuple_filter {
200  uint16_t flags;
201  uint32_t dst_ip;
202  uint32_t dst_ip_mask;
203  uint32_t src_ip;
204  uint32_t src_ip_mask;
205  uint16_t dst_port;
206  uint16_t dst_port_mask;
207  uint16_t src_port;
208  uint16_t src_port_mask;
209  uint8_t proto;
210  uint8_t proto_mask;
214  uint8_t tcp_flags;
215  uint16_t priority;
217  uint16_t queue;
218 };
219 
223 enum rte_eth_tunnel_type {
224  RTE_TUNNEL_TYPE_NONE = 0,
225  RTE_TUNNEL_TYPE_VXLAN,
226  RTE_TUNNEL_TYPE_GENEVE,
227  RTE_TUNNEL_TYPE_TEREDO,
228  RTE_TUNNEL_TYPE_NVGRE,
229  RTE_TUNNEL_TYPE_IP_IN_GRE,
230  RTE_L2_TUNNEL_TYPE_E_TAG,
231  RTE_TUNNEL_TYPE_MAX,
232 };
233 
237 #define ETH_TUNNEL_FILTER_OMAC 0x01
238 #define ETH_TUNNEL_FILTER_OIP 0x02
239 #define ETH_TUNNEL_FILTER_TENID 0x04
240 #define ETH_TUNNEL_FILTER_IMAC 0x08
241 #define ETH_TUNNEL_FILTER_IVLAN 0x10
242 #define ETH_TUNNEL_FILTER_IIP 0x20
244 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
245  ETH_TUNNEL_FILTER_IVLAN)
246 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
247  ETH_TUNNEL_FILTER_IVLAN | \
248  ETH_TUNNEL_FILTER_TENID)
249 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
250  ETH_TUNNEL_FILTER_TENID)
251 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
252  ETH_TUNNEL_FILTER_TENID | \
253  ETH_TUNNEL_FILTER_IMAC)
254 
258 enum rte_tunnel_iptype {
259  RTE_TUNNEL_IPTYPE_IPV4 = 0,
260  RTE_TUNNEL_IPTYPE_IPV6,
261 };
262 
266 struct rte_eth_tunnel_filter_conf {
267  struct ether_addr outer_mac;
268  struct ether_addr inner_mac;
269  uint16_t inner_vlan;
270  enum rte_tunnel_iptype ip_type;
274  union {
275  uint32_t ipv4_addr;
276  uint32_t ipv6_addr[4];
277  } ip_addr;
279  uint16_t filter_type;
280  enum rte_eth_tunnel_type tunnel_type;
281  uint32_t tenant_id;
282  uint16_t queue_id;
283 };
284 
288 enum rte_eth_global_cfg_type {
289  RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
290  RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
291  RTE_ETH_GLOBAL_CFG_TYPE_MAX,
292 };
293 
297 struct rte_eth_global_cfg {
298  enum rte_eth_global_cfg_type cfg_type;
299  union {
300  uint8_t gre_key_len;
301  uint64_t reserved;
302  } cfg;
303 };
304 
305 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
306 #define RTE_ETH_INSET_SIZE_MAX 128
311 enum rte_eth_input_set_field {
312  RTE_ETH_INPUT_SET_UNKNOWN = 0,
313 
314  /* L2 */
315  RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
316  RTE_ETH_INPUT_SET_L2_DST_MAC,
317  RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
318  RTE_ETH_INPUT_SET_L2_INNER_VLAN,
319  RTE_ETH_INPUT_SET_L2_ETHERTYPE,
320 
321  /* L3 */
322  RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
323  RTE_ETH_INPUT_SET_L3_DST_IP4,
324  RTE_ETH_INPUT_SET_L3_SRC_IP6,
325  RTE_ETH_INPUT_SET_L3_DST_IP6,
326  RTE_ETH_INPUT_SET_L3_IP4_TOS,
327  RTE_ETH_INPUT_SET_L3_IP4_PROTO,
328  RTE_ETH_INPUT_SET_L3_IP6_TC,
329  RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
330  RTE_ETH_INPUT_SET_L3_IP4_TTL,
331  RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
332 
333  /* L4 */
334  RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
335  RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
336  RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
337  RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
338  RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
339  RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
340  RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
341 
342  /* Tunnel */
343  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
344  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
345  RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
346  RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
347  RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
348 
349  /* Flexible Payload */
350  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
351  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
352  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
353  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
354  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
355  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
356  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
357  RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
358 
359  RTE_ETH_INPUT_SET_DEFAULT = 65533,
360  RTE_ETH_INPUT_SET_NONE = 65534,
361  RTE_ETH_INPUT_SET_MAX = 65535,
362 };
363 
367 enum rte_filter_input_set_op {
368  RTE_ETH_INPUT_SET_OP_UNKNOWN,
369  RTE_ETH_INPUT_SET_SELECT,
370  RTE_ETH_INPUT_SET_ADD,
371  RTE_ETH_INPUT_SET_OP_MAX
372 };
373 
374 
379 struct rte_eth_input_set_conf {
380  uint16_t flow_type;
381  uint16_t inset_size;
382  enum rte_eth_input_set_field field[RTE_ETH_INSET_SIZE_MAX];
383  enum rte_filter_input_set_op op;
384 };
385 
389 struct rte_eth_l2_flow {
390  uint16_t ether_type;
391 };
392 
396 struct rte_eth_ipv4_flow {
397  uint32_t src_ip;
398  uint32_t dst_ip;
399  uint8_t tos;
400  uint8_t ttl;
401  uint8_t proto;
402 };
403 
407 struct rte_eth_udpv4_flow {
408  struct rte_eth_ipv4_flow ip;
409  uint16_t src_port;
410  uint16_t dst_port;
411 };
412 
416 struct rte_eth_tcpv4_flow {
417  struct rte_eth_ipv4_flow ip;
418  uint16_t src_port;
419  uint16_t dst_port;
420 };
421 
425 struct rte_eth_sctpv4_flow {
426  struct rte_eth_ipv4_flow ip;
427  uint16_t src_port;
428  uint16_t dst_port;
429  uint32_t verify_tag;
430 };
431 
435 struct rte_eth_ipv6_flow {
436  uint32_t src_ip[4];
437  uint32_t dst_ip[4];
438  uint8_t tc;
439  uint8_t proto;
440  uint8_t hop_limits;
441 };
442 
446 struct rte_eth_udpv6_flow {
447  struct rte_eth_ipv6_flow ip;
448  uint16_t src_port;
449  uint16_t dst_port;
450 };
451 
455 struct rte_eth_tcpv6_flow {
456  struct rte_eth_ipv6_flow ip;
457  uint16_t src_port;
458  uint16_t dst_port;
459 };
460 
464 struct rte_eth_sctpv6_flow {
465  struct rte_eth_ipv6_flow ip;
466  uint16_t src_port;
467  uint16_t dst_port;
468  uint32_t verify_tag;
469 };
470 
474 struct rte_eth_mac_vlan_flow {
475  struct ether_addr mac_addr;
476 };
477 
481 enum rte_eth_fdir_tunnel_type {
482  RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
483  RTE_FDIR_TUNNEL_TYPE_NVGRE,
484  RTE_FDIR_TUNNEL_TYPE_VXLAN,
485 };
486 
491 struct rte_eth_tunnel_flow {
492  enum rte_eth_fdir_tunnel_type tunnel_type;
494  uint32_t tunnel_id;
495  struct ether_addr mac_addr;
496 };
497 
502 union rte_eth_fdir_flow {
503  struct rte_eth_l2_flow l2_flow;
504  struct rte_eth_udpv4_flow udp4_flow;
505  struct rte_eth_tcpv4_flow tcp4_flow;
506  struct rte_eth_sctpv4_flow sctp4_flow;
507  struct rte_eth_ipv4_flow ip4_flow;
508  struct rte_eth_udpv6_flow udp6_flow;
509  struct rte_eth_tcpv6_flow tcp6_flow;
510  struct rte_eth_sctpv6_flow sctp6_flow;
511  struct rte_eth_ipv6_flow ipv6_flow;
512  struct rte_eth_mac_vlan_flow mac_vlan_flow;
513  struct rte_eth_tunnel_flow tunnel_flow;
514 };
515 
519 struct rte_eth_fdir_flow_ext {
520  uint16_t vlan_tci;
521  uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
523  uint8_t is_vf;
524  uint16_t dst_id;
525 };
526 
530 struct rte_eth_fdir_input {
531  uint16_t flow_type;
532  union rte_eth_fdir_flow flow;
534  struct rte_eth_fdir_flow_ext flow_ext;
536 };
537 
541 enum rte_eth_fdir_behavior {
542  RTE_ETH_FDIR_ACCEPT = 0,
543  RTE_ETH_FDIR_REJECT,
544  RTE_ETH_FDIR_PASSTHRU,
545 };
546 
551 enum rte_eth_fdir_status {
552  RTE_ETH_FDIR_NO_REPORT_STATUS = 0,
553  RTE_ETH_FDIR_REPORT_ID,
554  RTE_ETH_FDIR_REPORT_ID_FLEX_4,
555  RTE_ETH_FDIR_REPORT_FLEX_8,
556 };
557 
561 struct rte_eth_fdir_action {
562  uint16_t rx_queue;
563  enum rte_eth_fdir_behavior behavior;
564  enum rte_eth_fdir_status report_status;
565  uint8_t flex_off;
569 };
570 
576 struct rte_eth_fdir_filter {
577  uint32_t soft_id;
579  struct rte_eth_fdir_input input;
580  struct rte_eth_fdir_action action;
581 };
582 
587 struct rte_eth_fdir_masks {
588  uint16_t vlan_tci_mask;
590  struct rte_eth_ipv4_flow ipv4_mask;
592  struct rte_eth_ipv6_flow ipv6_mask;
594  uint16_t src_port_mask;
596  uint16_t dst_port_mask;
599  uint8_t mac_addr_byte_mask;
601  uint32_t tunnel_id_mask;
602  uint8_t tunnel_type_mask;
604 };
605 
609 enum rte_eth_payload_type {
610  RTE_ETH_PAYLOAD_UNKNOWN = 0,
611  RTE_ETH_RAW_PAYLOAD,
612  RTE_ETH_L2_PAYLOAD,
613  RTE_ETH_L3_PAYLOAD,
614  RTE_ETH_L4_PAYLOAD,
615  RTE_ETH_PAYLOAD_MAX = 8,
616 };
617 
622 struct rte_eth_flex_payload_cfg {
623  enum rte_eth_payload_type type;
624  uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN];
629 };
630 
635 struct rte_eth_fdir_flex_mask {
636  uint16_t flow_type;
637  uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN];
639 };
640 
645 struct rte_eth_fdir_flex_conf {
646  uint16_t nb_payloads;
647  uint16_t nb_flexmasks;
648  struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
650  struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
652 };
653 
657 enum rte_fdir_mode {
658  RTE_FDIR_MODE_NONE = 0,
659  RTE_FDIR_MODE_SIGNATURE,
660  RTE_FDIR_MODE_PERFECT,
661  RTE_FDIR_MODE_PERFECT_MAC_VLAN,
662  RTE_FDIR_MODE_PERFECT_TUNNEL,
663 };
664 
665 #define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
666 #define RTE_FLOW_MASK_ARRAY_SIZE \
667  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
668 
676 struct rte_eth_fdir_info {
677  enum rte_fdir_mode mode;
678  struct rte_eth_fdir_masks mask;
680  struct rte_eth_fdir_flex_conf flex_conf;
681  uint32_t guarant_spc;
682  uint32_t best_spc;
684  uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
685  uint32_t max_flexpayload;
688  uint32_t flex_payload_unit;
691  uint32_t max_flex_payload_segment_num;
695  uint16_t flex_payload_limit;
698  uint32_t flex_bitmask_unit;
700  uint32_t max_flex_bitmask_num;
701 };
702 
707 struct rte_eth_fdir_stats {
708  uint32_t collision;
709  uint32_t free;
710  uint32_t maxhash;
713  uint32_t maxlen;
714  uint64_t add;
715  uint64_t remove;
716  uint64_t f_add;
717  uint64_t f_remove;
718  uint32_t guarant_cnt;
719  uint32_t best_cnt;
720 };
721 
725 enum rte_eth_fdir_filter_info_type {
726  RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
728  RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT,
729  RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
730 };
731 
736 struct rte_eth_fdir_filter_info {
737  enum rte_eth_fdir_filter_info_type info_type;
739  union {
741  struct rte_eth_input_set_conf input_set_conf;
742  } info;
743 };
744 
755 enum rte_eth_hash_filter_info_type {
756  RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
758  RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT,
760  RTE_ETH_HASH_FILTER_GLOBAL_CONFIG,
762  RTE_ETH_HASH_FILTER_INPUT_SET_SELECT,
763  RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
764 };
765 
769 enum rte_eth_hash_function {
770  RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
771  RTE_ETH_HASH_FUNCTION_TOEPLITZ,
772  RTE_ETH_HASH_FUNCTION_SIMPLE_XOR,
773  RTE_ETH_HASH_FUNCTION_MAX,
774 };
775 
776 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \
777  (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
778 
787 struct rte_eth_hash_global_conf {
788  enum rte_eth_hash_function hash_func;
790  uint64_t sym_hash_enable_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
792  uint64_t valid_bit_mask[RTE_SYM_HASH_MASK_ARRAY_SIZE];
793 };
794 
799 struct rte_eth_hash_filter_info {
800  enum rte_eth_hash_filter_info_type info_type;
802  union {
804  uint8_t enable;
806  struct rte_eth_hash_global_conf global_conf;
808  struct rte_eth_input_set_conf input_set_conf;
809  } info;
810 };
811 
815 struct rte_eth_l2_tunnel_conf {
816  enum rte_eth_tunnel_type l2_tunnel_type;
817  uint16_t ether_type; /* ether type in l2 header */
818  uint32_t tunnel_id; /* port tag id for e-tag */
819  uint16_t vf_id; /* VF id for tag insertion */
820  uint32_t pool; /* destination pool for tag based forwarding */
821 };
822 
823 #ifdef __cplusplus
824 }
825 #endif
826 
827 #endif /* _RTE_ETH_CTRL_H_ */
Generated by   doxygen 1.8.1.2