34 #ifndef _RTE_ETH_CTRL_H_
35 #define _RTE_ETH_CTRL_H_
59 #define RTE_ETH_FLOW_UNKNOWN 0
60 #define RTE_ETH_FLOW_RAW 1
61 #define RTE_ETH_FLOW_IPV4 2
62 #define RTE_ETH_FLOW_FRAG_IPV4 3
63 #define RTE_ETH_FLOW_NONFRAG_IPV4_TCP 4
64 #define RTE_ETH_FLOW_NONFRAG_IPV4_UDP 5
65 #define RTE_ETH_FLOW_NONFRAG_IPV4_SCTP 6
66 #define RTE_ETH_FLOW_NONFRAG_IPV4_OTHER 7
67 #define RTE_ETH_FLOW_IPV6 8
68 #define RTE_ETH_FLOW_FRAG_IPV6 9
69 #define RTE_ETH_FLOW_NONFRAG_IPV6_TCP 10
70 #define RTE_ETH_FLOW_NONFRAG_IPV6_UDP 11
71 #define RTE_ETH_FLOW_NONFRAG_IPV6_SCTP 12
72 #define RTE_ETH_FLOW_NONFRAG_IPV6_OTHER 13
73 #define RTE_ETH_FLOW_L2_PAYLOAD 14
74 #define RTE_ETH_FLOW_IPV6_EX 15
75 #define RTE_ETH_FLOW_IPV6_TCP_EX 16
76 #define RTE_ETH_FLOW_IPV6_UDP_EX 17
77 #define RTE_ETH_FLOW_MAX 18
83 RTE_ETH_FILTER_NONE = 0,
84 RTE_ETH_FILTER_MACVLAN,
85 RTE_ETH_FILTER_ETHERTYPE,
86 RTE_ETH_FILTER_FLEXIBLE,
88 RTE_ETH_FILTER_NTUPLE,
89 RTE_ETH_FILTER_TUNNEL,
92 RTE_ETH_FILTER_L2_TUNNEL,
110 RTE_ETH_FILTER_OP_MAX
138 #define RTE_ETHTYPE_FLAGS_MAC 0x0001
139 #define RTE_ETHTYPE_FLAGS_DROP 0x0002
146 struct rte_eth_ethertype_filter {
153 #define RTE_FLEX_FILTER_MAXLEN 128
154 #define RTE_FLEX_FILTER_MASK_SIZE \
155 (RTE_ALIGN(RTE_FLEX_FILTER_MAXLEN, CHAR_BIT) / CHAR_BIT)
187 #define RTE_NTUPLE_FLAGS_DST_IP 0x0001
188 #define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
189 #define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
190 #define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
191 #define RTE_NTUPLE_FLAGS_PROTO 0x0010
192 #define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
194 #define RTE_5TUPLE_FLAGS ( \
195 RTE_NTUPLE_FLAGS_DST_IP | \
196 RTE_NTUPLE_FLAGS_SRC_IP | \
197 RTE_NTUPLE_FLAGS_DST_PORT | \
198 RTE_NTUPLE_FLAGS_SRC_PORT | \
199 RTE_NTUPLE_FLAGS_PROTO)
201 #define RTE_2TUPLE_FLAGS ( \
202 RTE_NTUPLE_FLAGS_DST_PORT | \
203 RTE_NTUPLE_FLAGS_PROTO)
205 #define TCP_URG_FLAG 0x20
206 #define TCP_ACK_FLAG 0x10
207 #define TCP_PSH_FLAG 0x08
208 #define TCP_RST_FLAG 0x04
209 #define TCP_SYN_FLAG 0x02
210 #define TCP_FIN_FLAG 0x01
211 #define TCP_FLAG_ALL 0x3F
243 RTE_TUNNEL_TYPE_NONE = 0,
244 RTE_TUNNEL_TYPE_VXLAN,
245 RTE_TUNNEL_TYPE_GENEVE,
246 RTE_TUNNEL_TYPE_TEREDO,
247 RTE_TUNNEL_TYPE_NVGRE,
248 RTE_TUNNEL_TYPE_IP_IN_GRE,
249 RTE_L2_TUNNEL_TYPE_E_TAG,
256 #define ETH_TUNNEL_FILTER_OMAC 0x01
257 #define ETH_TUNNEL_FILTER_OIP 0x02
258 #define ETH_TUNNEL_FILTER_TENID 0x04
259 #define ETH_TUNNEL_FILTER_IMAC 0x08
260 #define ETH_TUNNEL_FILTER_IVLAN 0x10
261 #define ETH_TUNNEL_FILTER_IIP 0x20
263 #define RTE_TUNNEL_FILTER_IMAC_IVLAN (ETH_TUNNEL_FILTER_IMAC | \
264 ETH_TUNNEL_FILTER_IVLAN)
265 #define RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID (ETH_TUNNEL_FILTER_IMAC | \
266 ETH_TUNNEL_FILTER_IVLAN | \
267 ETH_TUNNEL_FILTER_TENID)
268 #define RTE_TUNNEL_FILTER_IMAC_TENID (ETH_TUNNEL_FILTER_IMAC | \
269 ETH_TUNNEL_FILTER_TENID)
270 #define RTE_TUNNEL_FILTER_OMAC_TENID_IMAC (ETH_TUNNEL_FILTER_OMAC | \
271 ETH_TUNNEL_FILTER_TENID | \
272 ETH_TUNNEL_FILTER_IMAC)
308 RTE_ETH_GLOBAL_CFG_TYPE_UNKNOWN = 0,
309 RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN,
310 RTE_ETH_GLOBAL_CFG_TYPE_MAX,
324 #define RTE_ETH_FDIR_MAX_FLEXLEN 16
325 #define RTE_ETH_INSET_SIZE_MAX 128
330 enum rte_eth_input_set_field {
331 RTE_ETH_INPUT_SET_UNKNOWN = 0,
334 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
335 RTE_ETH_INPUT_SET_L2_DST_MAC,
336 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
337 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
338 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
341 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
342 RTE_ETH_INPUT_SET_L3_DST_IP4,
343 RTE_ETH_INPUT_SET_L3_SRC_IP6,
344 RTE_ETH_INPUT_SET_L3_DST_IP6,
345 RTE_ETH_INPUT_SET_L3_IP4_TOS,
346 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
347 RTE_ETH_INPUT_SET_L3_IP6_TC,
348 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
349 RTE_ETH_INPUT_SET_L3_IP4_TTL,
350 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
353 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
354 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
355 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
356 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
357 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
358 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
359 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
362 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
363 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
364 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
365 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
366 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
369 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
370 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
371 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
372 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
373 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
374 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
375 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
376 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
378 RTE_ETH_INPUT_SET_DEFAULT = 65533,
379 RTE_ETH_INPUT_SET_NONE = 65534,
380 RTE_ETH_INPUT_SET_MAX = 65535,
387 RTE_ETH_INPUT_SET_OP_UNKNOWN,
390 RTE_ETH_INPUT_SET_OP_MAX
501 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
502 RTE_FDIR_TUNNEL_TYPE_NVGRE,
503 RTE_FDIR_TUNNEL_TYPE_VXLAN,
561 RTE_ETH_FDIR_ACCEPT = 0,
563 RTE_ETH_FDIR_PASSTHRU,
629 RTE_ETH_PAYLOAD_UNKNOWN = 0,
634 RTE_ETH_PAYLOAD_MAX = 8,
684 #define UINT32_BIT (CHAR_BIT * sizeof(uint32_t))
685 #define RTE_FLOW_MASK_ARRAY_SIZE \
686 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)
745 RTE_ETH_FDIR_FILTER_INFO_TYPE_UNKNOWN = 0,
748 RTE_ETH_FDIR_FILTER_INFO_TYPE_MAX,
775 RTE_ETH_HASH_FILTER_INFO_TYPE_UNKNOWN = 0,
782 RTE_ETH_HASH_FILTER_INFO_TYPE_MAX,
789 RTE_ETH_HASH_FUNCTION_DEFAULT = 0,
792 RTE_ETH_HASH_FUNCTION_MAX,
795 #define RTE_SYM_HASH_MASK_ARRAY_SIZE \
796 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT32_BIT)/UINT32_BIT)